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nuc123 may 3 , 201 7 page 1 of 99 rev. 2 . 0 4 nuc123 series datasheet arm ? c ortex ? - m 0 32 - bit microcontroller numicr o ? fa mily nuc123 series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
nuc123 may 3 , 201 7 page 2 of 99 rev. 2 . 0 4 nuc123 series datasheet table of contents list of figures ................................ ................................ .............................. 6 list of tables ................................ ................................ ............................... 7 1 general description ................................ ................................ ....... 8 2 features ................................ ................................ ......................... 9 numicro ? nuc123 series features ................................ ................................ 9 2.1 3 abbreviations ................................ ................................ ..................... 12 4 parts information list and pin configuration .............................. 14 numicro ? nuc123 series naming rule ................................ .......................... 14 4.1 numicro ? nuc123 series selection guide ................................ ....................... 15 4.2 4.2.1 numicro ? nuc123xxxanx selection guide ................................ .............................. 15 4.2.2 numicro ? nuc123xxxaex selection guide ................................ .............................. 15 numicro ? nuc123 series pin configuration ................................ ..................... 16 4.3 4.3.1 numicro ? nuc123xxxanx pin diagram ................................ ................................ .. 16 4.3.2 numicro ? nuc123xxxaex pin diagram ................................ ................................ .. 19 pin description ................................ ................................ ........................ 22 4.4 4.4.1 numicro ? nuc123 pin description ................................ ................................ ........ 22 5 block diagram ................................ ................................ ............... 27 numicro ? nuc123 block diagram ................................ ................................ . 27 5.1 6 functional description ................................ ................................ . 28 arm ? cortex ? - m0 core ................................ ................................ .............. 28 6.1 system manager ................................ ................................ ...................... 30 6.2 6.2.1 overview ................................ ................................ ................................ ....... 30 6.2.2 system reset ................................ ................................ ................................ .. 30 6.2.3 power modes and wake - up sources ................................ ................................ ...... 36 6.2.4 system power distribution ................................ ................................ .................. 3 9 6.2.5 system memory map ................................ ................................ ......................... 40 6.2.6 system timer (systick) ................................ ................................ ..................... 42 6.2.7 nested vectored interrupt controller (nvic) ................................ ............................. 43 clock controller ................................ ................................ ....................... 47 6.3 6.3.1 overview ................................ ................................ ................................ ....... 47 6.3.2 system clock and systick clock ................................ ................................ .......... 50 6.3.3 peripherals clock ................................ ................................ ............................. 50
nuc123 may 3 , 201 7 page 3 of 99 rev. 2 . 0 4 nuc123 series datasheet 6.3.4 power - down mode clock ................................ ................................ .................... 50 6.3.5 frequency divider output ................................ ................................ ................... 51 flash memory controller (fmc) ................................ ................................ .... 52 6.4 6.4.1 overview ................................ ................................ ................................ ....... 52 6.4.2 features ................................ ................................ ................................ ........ 52 general purpose i/o (gpio) ................................ ................................ ........ 53 6.5 6.5.1 overview ................................ ................................ ................................ ....... 53 6.5.2 features ................................ ................................ ................................ ........ 53 pdma controller (pdma) ................................ ................................ ........... 54 6.6 6.6.1 overview ................................ ................................ ................................ ....... 54 6.6.2 features ................................ ................................ ................................ ........ 54 timer controller (tmr) ................................ ................................ .............. 55 6.7 6.7.1 overview ................................ ................................ ................................ ....... 55 6.7.2 features ................................ ................................ ................................ ........ 55 pwm generator and capture timer (pwm) ................................ ..................... 56 6.8 6.8.1 overview ................................ ................................ ................................ ....... 56 6.8.2 features ................................ ................................ ................................ ........ 56 watchdog timer (wdt) ................................ ................................ .............. 57 6.9 6.9.1 overview ................................ ................................ ................................ ....... 57 6.9.2 features ................................ ................................ ................................ ........ 57 window watchdog timer (wwdt) ................................ ................................ 58 6.10 6.10.1 overview ................................ ................................ ................................ ....... 58 6.10.2 featu res ................................ ................................ ................................ ........ 58 uart interface controller (uart) ................................ ................................ . 59 6.11 6.11.1 overview ................................ ................................ ................................ ....... 59 6.11.2 features ................................ ................................ ................................ ........ 59 ps/2 device controller (ps2d) ................................ ................................ ..... 60 6.12 6.12.1 overview ................................ ................................ ................................ ....... 60 6.12.2 features ................................ ................................ ................................ ........ 60 i 2 c serial interface controller (master/slave) (i 2 c) ................................ .............. 61 6.13 6.13.1 overview ................................ ................................ ................................ ....... 61 6.13.2 features ................................ ................................ ................................ ........ 61 serial peripheral interface (spi) ................................ ................................ .... 62 6.14 6.14.1 overview ................................ ................................ ................................ ....... 62 6.14.2 features ................................ ................................ ................................ ........ 62
nuc123 may 3 , 201 7 page 4 of 99 rev. 2 . 0 4 nuc123 series datasheet i 2 s controller (i 2 s) ................................ ................................ .................... 63 6.15 6.15.1 overview ................................ ................................ ................................ ....... 63 6.15.2 features ................................ ................................ ................................ ........ 63 usb device controller (usb) ................................ ................................ ....... 64 6.16 6.16.1 overview ................................ ................................ ................................ ....... 64 6.16.2 features ................................ ................................ ................................ ........ 64 analog - to - digital converter (adc) ................................ ................................ . 65 6.17 6.17.1 overview ................................ ................................ ................................ ....... 65 6.17.2 features ................................ ................................ ................................ ........ 65 7 electrical characteristics (nuc123xxxanx) ................................ ... 66 absolute maximum ratings ................................ ................................ ......... 66 7.1 dc electrical characteristics ................................ ................................ ........ 67 7.2 ac electrical characteristics ................................ ................................ ........ 71 7.3 7.3.1 external 4~24 mhz high speed oscillator ................................ ............................... 71 7.3.2 external 4~24 mhz high speed crystal ................................ ................................ .. 71 7.3.3 internal 22.1184 mhz high speed oscillator ................................ ............................. 72 7.3.4 internal 10 khz low speed oscillator ................................ ................................ ..... 72 analog characteristics ................................ ................................ ............... 73 7.4 7.4.1 10 - bit saradc specifications ................................ ................................ .............. 73 7.4.2 ldo and power management specifications ................................ ............................ 74 7.4.3 low voltage reset specifications ................................ ................................ .......... 74 7.4.4 brown - out detector specifications ................................ ................................ ......... 75 7.4.5 power - on reset (5v) specifications ................................ ................................ ...... 75 7.4.6 usb phy specifications ................................ ................................ ..................... 76 flash dc electrical characteristics ................................ ................................ 77 7.5 spi dynamic characteristics ................................ ................................ ........ 78 7.6 8 electrical characteristics (nuc123xxxaex) ................................ .... 80 absolute maximum ratings ................................ ................................ ......... 80 8.1 dc electrical characteristics ................................ ................................ ........ 81 8.2 ac electrical characteristics ................................ ................................ ........ 85 8.3 8.3.1 external 4~24 mhz high speed oscillator ................................ ............................... 85 8.3.2 external 4~24 mhz high speed crystal ................................ ................................ .. 85 8.3.3 internal 22.1184 mhz high speed oscillator ................................ ............................. 86 8.3.4 internal 10 khz low speed oscillator ................................ ................................ ..... 86 analog characteristics ................................ ................................ ............... 87 8.4
nuc123 may 3 , 201 7 page 5 of 99 rev. 2 . 0 4 nuc123 series datasheet 8.4.1 10 - bit saradc specifications ................................ ................................ .............. 87 8.4.2 ldo and power management specifications ................................ ............................ 88 8.4.3 low voltage reset specifications ................................ ................................ .......... 88 8.4.4 brown - out detector specifications ................................ ................................ ......... 89 8.4.5 power - on reset (5v) specifications ................................ ................................ ...... 89 8.4.6 usb phy specifications ................................ ................................ ..................... 90 flash dc electrical characteristics ................................ ................................ 92 8.5 spi dynamic characteristics ................................ ................................ ........ 93 8.6 9 package dimensions ................................ ................................ ...... 95 64l lqfp (7x7x1.4 mm footprint 2.0 mm) ................................ ........................ 95 9.1 48l lqfp (7x7x1.4 mm footprint 2.0 mm) ................................ ........................ 96 9.2 33l qfn (5x5x0.8 mm) ................................ ................................ .............. 97 9.3 10 r evision history ................................ ................................ ............ 98
nuc123 may 3 , 201 7 page 6 of 99 rev. 2 . 0 4 nuc123 series datasheet list of figure s figure 4 - 1 numicro ? nuc123 series selection code ................................ ................................ ... 14 figure 4 - 2 numicro ? nuc123sxxanx lqfp 64 - pin diagram ................................ ....................... 16 figure 4 - 3 numicro ? nuc123lxxanx lqfp 48 - pin diagram ................................ ....................... 17 figure 4 - 4 numicro ? nuc123zxxanx qfn 33 - pin diagram ................................ ......................... 18 figure 4 - 5 numicro ? nuc123sxxaex lqfp 64 - pin diagram ................................ ....................... 19 figure 4 - 6 numicro ? nuc123lxxaex lqfp 48 - pin diagram ................................ ....................... 20 figure 4 - 7 numicro ? nuc123zxxaex qfn 33 - pin diagram ................................ ......................... 21 figure 5 - 1 numicro ? nuc123 block diagram ................................ ................................ ............... 27 figure 6 - 1 functional controller diagram ................................ ................................ ...................... 28 figure 6 - 2 system reset resources ................................ ................................ ............................. 31 figure 6 - 3 nreset reset waveform ................................ ................................ ............................ 33 figure 6 - 4 power - on reset (por) waveform ................................ ................................ ............... 34 figure 6 - 5 low voltage reset waveform ................................ ................................ ...................... 34 figure 6 - 6 brown - out detector waveform ................................ ................................ .................... 35 figure 6 - 7 power mode state machine ................................ ................................ ......................... 36 figure 6 - 8 numicro ? nuc123 power distribution diagram ................................ ........................... 39 figure 6 - 9 clock generator global view diagram ................................ ................................ ......... 48 figure 6 - 10 clock generator global view diagram ................................ ................................ ....... 49 figure 6 - 11 system clock block diagram ................................ ................................ ..................... 50 figure 6 - 12 systick clock control block diagram ................................ ................................ ........ 50 figure 6 - 13 clock source of frequency divider ................................ ................................ ............ 51 figure 6 - 14 block diagram of frequency divider ................................ ................................ .......... 51 figure 7 - 1 typical crystal application circuit ................................ ................................ ................ 71 figure 7 - 2 spi master dynamic characteristics timing ................................ ................................ 78 figure 7 - 3 spi slave dynamic characteristics timing ................................ ................................ .. 79 figure 8 - 1 typical crystal application circuit ................................ ................................ ................ 85 figure 8 - 2 spi master dynamic characteristics timing ................................ ................................ . 93 figure 8 - 3 spi slave dynamic characteristics timing ................................ ................................ .. 94
nuc123 may 3 , 201 7 page 7 of 99 rev. 2 . 0 4 nuc123 series datasheet list of tables table 1 - 1 key features support table ................................ ................................ ............................ 8 table 3 - 1 list of abbreviations ................................ ................................ ................................ ....... 13 table 6 - 1 reset value of registers ................................ ................................ ............................... 32 table 6 - 2 power mode differe nce table ................................ ................................ ....................... 36 table 6 - 3 c lock s in power modes ................................ ................................ ................................ . 37 table 6 - 4 condition of entering power - down mode again ................................ ............................ 38 table 6 - 5 address space assignments for on - chip controllers ................................ ................... 41 table 6 - 6 exception model ................................ ................................ ................................ ............ 44 table 6 - 7 system interrupt map ................................ ................................ ................................ ..... 45 table 6 - 8 vector table format ................................ ................................ ................................ ...... 46 table 6 - 9 clock stable count value table ................................ ................................ .................... 47
nuc123 may 3 , 201 7 page 8 of 99 rev. 2 . 0 4 nuc123 series datasheet 1 general description the numicro ? nuc123 series is a new 32 - bit cortex ? - m0 microcontroller with usb 2.0 full - s peed devices and a 10 - bit adc. the nuc123 series provides the high 72 mhz ope rating speed, large 20 kbytes sram, 8 usb endpoints and three sets of spi controllers, w hich make it powerful in usb communication and data processing. the nuc123 series is ideal for industrial control , consumer electronics , and communication system applications such as printers , touch panel, gaming keyboard, gaming joystick, usb audio, pc peripherals , and alarm systems . the nuc123 series run s up to 72 mhz and supports 32 - bit multiplier, structure nvic (nested vector interrupt control), dual - channel a pb and pdma (peripheral direct memory access) with crc function. besides , the nuc123 series is equipped with 36 / 68 kbytes f lash memory, 12 / 20 kbytes sram , and 4 kbytes loader rom for the isp . it operate s at a wide voltage range of 2.5v ~ 5.5v and temperatu re range of - 40 ~ +105 and - 40 ~ + 8 5 . it is also equipped with plenty of peripheral devices, such as 8 - channel 10 - bit adc, uart, spi, i 2 c, i 2 s , usb 2.0 fs devices, and offers low - voltage reset and brown - out detection, pwm (pulse - width modulation), capture and compare features, four sets of 32 - bit timers, watchdog timer, and internal rc oscillator. all these peripherals have been incorporated into the nuc123 series to reduce component count, board space and system cost. additionally, the nuc123 series is equipped with isp (in - system programming) , iap ( in - application - programming ) and icp (in - circuit programming) functions, which allow s the user to u pdate the program under software control through the on - chip connectivity interface, such as swd, uart and usb . product line uart spi i 2 c usb ps / 2 i 2 s pwm adc nuc12 3 2 3 2 1 1 1 4 8 table 1 - 1 key features support table
nuc123 may 3 , 201 7 page 9 of 99 rev. 2 . 0 4 nuc123 series datasheet 2 features numicro ? nuc123 series features 2.1 ? core C arm ? cortex ? - m0 core r uns up to 72 mhz C one 24 - bit system timer C supports low power sleep mode C single - cycle 32 - bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4 - levels of priority C supports serial wire debug with 2 watchpoints/4 breakpoints ? buil t - in ldo for wide operating voltage ranges from 2.5 v to 5.5 v ? flash memory C 3 6 / 68 k b flash for program code C 4 kb flash for isp loader C support s in - s ystem p rogram (isp) application code update C 512 byte page erase for flash C configurable data flash address and size for both 36kb and 68kb system C support s 2 - wire icp update through swd/ice interface C support s fast parallel programming mode by external programmer ? sram memory C 12 / 20 k b embedded sram C support s pdma mode ? pdma (peripheral dma) C support s 6 channels pdma for automatic data transfer between sram and peripherals such as spi, uart, i 2 s , usb 2.0 fs device, pwm and adc C support s crc calculation with four common polynomials, crc - ccitt, crc - 8, crc - 16 and crc - 32 ? clock control C flexible selection for different applications C buil t - in 22.1184 mhz high speed oscillator (trimmed to 1%) for system operation, and low power 10 khz low speed o scillator for watchdog and wake - up operation C support s one pll, up to 144 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for precise timing operation ? gpio C four i/o modes: ? quasi bi - direction ? push - pull output ? open - drain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin configured as interrupt source with edge/level setting C supports high d river and h igh s ink i/o mode ? timer C support s 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit pre - scale counter C independent clock source for each timer C provides one - shot, periodic, toggle and continuous counting operation modes C support s event counting function ? watchdog /windowed - watchdog t imer C multiple clock sources
nuc123 may 3 , 201 7 page 10 of 99 rev. 2 . 0 4 nuc123 series datasheet C 8 selectable time - out period from 1. 6ms ~ 26 .0sec (depend ing on clock source) C w ake - up from p ower - down or idle mode C interrupt or reset selectable on watchdog timer time - out C interrupt on windowed - watchdog timer time - out C reset on windowed - watchdog timer time - out or reload in an unexpected time window ? pwm /capture C u p to two b uilt - in 16 - bit pwm generators provid ed with four pwm outputs or two complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8 - bit prescaler and one dead - zone generator for complementary paired pwm C up to four 16 - bit digital capture timers (shared with pwm timers) provide d with four rising/falling capture inputs C support s capture interrupt ? uart C up to two uart controllers C uart ports with flow control (txd, rxd, cts and rts) C uart 0 / 1 with 1 6 - byte fifo for standard device C support irda (sir) function C support s rs - 485 9 - bit mode and direction control. C programmable baud - rate generator up to 1/16 system clock C support s pdma mode ? spi C up to three sets of spi controller s C support s spi master/ slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 8 to 32 bit s C msb or lsb fi rst data transfer C up to t wo slave/device select lines in m aster mode C support s b yte s uspend mode in 16/24/ 32 - bit transmission C support s pdma transfer ? i 2 c C up to two sets of i 2 c device s C master/ slave mode C bidirectional data transfer between masters and slaves C multi - master bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock sy nchronization used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow ing versatile rate control C support s multiple address recognition (four slave address with mask option) C support s wake - up by address recognition (for 1 st slave address only) ? i 2 s C interface with external audio codec C operate d as either master or slave mode C capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes C supports mono and stereo audio data C supports i 2 s and msb justified data format C two 8 word fifo data buffers are provided, one for transmit ting and the other for receiv ing
nuc123 may 3 , 201 7 page 11 of 99 rev. 2 . 0 4 nuc123 series datasheet C generates interrupt requests when buffer levels cross a programmable boundary C support s two dma requests, one for transmit ting and the other for receiv ing ? p s/ 2 device controller C hos t communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C s/w override bus ? usb 2.0 full - speed device C one set of usb 2.0 fs device 12 mbps C on - chip usb t ransceiver C provide s 1 interrupt source with 4 interrupt event s C support s control, bulk in/out, interrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms C provide s 8 programmable endpoints C include s 512 bytes internal sram as usb buffer C provide s remote wake - up capability ? adc C 1 0 - bit sar adc with 15 0k sps (for nuc123xxxanx ) C 1 0 - bit sar adc with 200 k sps (for nuc123xxxaex ) C up to 8 - ch single - end input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start by software programming or external input C support s pdma mode ? brown - out detector C with 4 levels: 4. 4 v/3. 7 v/2.7 v/2.2 v C support s brown - out interrupt and reset option ? low voltage reset C threshold voltage levels: 2.0 v ? one built - in ldo ? operating temperature: - 40 ~85 (for nuc123xxxanx ) ? operating temperature: - 40 ~ 10 5 (for nuc123xxxaex ) ? packages: C all green package (rohs) C lqfp 64 - pin C lqfp 48 - pin C qfn 33 - pin
nuc123 may 3 , 201 7 page 12 of 99 rev. 2 . 0 4 nuc123 series datasheet 3 abbreviations acronym description acmp analog comparator controller adc analog - to - digital converter aes advanced encryption standard apb advanced peripheral bus ahb a dvanced h igh - p erformance b us bod brown - out detection can controller area network dap debug access port des data encryption standard ebi external bus interface epwm enhanced pulse width modulation fifo first in, first out fmc flash memory controller fpu floating - point unit gpio general - purpose input/output hclk the clock of a dvanced h igh - p erformance b us hirc 22.1184 mhz i nternal h igh s peed rc o scillator hxt 4~20 mhz e xternal h igh s peed c rystal o scillator iap in application programming icp in circuit programming isp in system programming ldo low dropout regulator lin local interconnect network lirc 10 khz internal low speed rc oscillator (lirc) mpu memory protection unit nvic nested vectored interrupt controller pclk the clock of advanced peripheral bus pdma peripheral direct memory access pll phase - locked loop pwm pulse width modulation qei quadrature encoder interface sd secure digital spi serial peripheral interface
nuc123 may 3 , 201 7 page 13 of 99 rev. 2 . 0 4 nuc123 series datasheet sps samples per second tdes triple data encryption standard tk touch key tmr timer controller uart universal asynchronous receiver/transmitter ucid unique customer id usb universal serial bus wdt watchdog timer wwdt window watchdog timer table 3 - 1 list of abbreviations
nuc123 may 3 , 201 7 page 14 of 99 rev. 2 . 0 4 nuc123 series datasheet 4 parts information li st and pin configuration numicro ? nuc 123 series naming rule 4.1 figure 4 - 1 numicro ? nuc123 series selection code n u c a r m C ? - m 0 5 / 7 : a r m 7 9 : a r m 9 p r o d u c t l i n e f u n c t i o n 1 2 3 - x x x x x x 0 : a d v a n c e l i n e 2 : u s b l i n e 3 : a u t o m o t i v e l i n e 4 : c o n n e c t i v i t y l i n e 5 : h i g h d e n s i t y r e s e r v e d 0 ~ 9 : s u b p r o d u c t l i n e p a c k a g e t y p e z : q f n 3 3 5 x 5 m m l : l q f p 4 8 7 x 7 m m s : l q f p 6 4 7 x 7 m m o p t i o n 0 : s r a m 2 0 k b 1 : s r a m 1 2 k b t e m p e r a t u r e n : - 4 0 o c ~ + 8 5 o c e : - 4 0 o c ~ + 1 0 5 o c r e s e r v e d s r a m s i z e 2 : 1 2 k b 4 : 2 0 k b f l a s h r o m c : 3 6 k b d : 6 8 k b
nuc123 may 3 , 201 7 page 15 of 99 rev. 2 . 0 4 nuc123 series datasheet numicro ? nuc 12 3 series selection guide 4.2 4.2.1 numicro ? nuc123 xxxanx selection guide part number flash (kb) sram (kb) isp rom (kb) i/o timer connectivity i 2 s comp. pwm adc rtc ebi isp \ icp \ iap 1.8v power pin package uart spi i 2 c usb lin ps/2 nuc1 2 3zd4 an 0 68 20 4 up to 20 4 x 32 - bit 1 3 1 1 - - 1 - 2 3 x 10 - bit - - v - qfn33 nuc1 2 3zc2 an 1 36 12 4 up to 20 4 x 32 - bit 1 3 1 1 - - 1 - 2 3 x 10 - bit - - v - qfn33 nuc1 2 3ld4 an 0 6 8 20 4 up to 36 4 x 32 - bit 2 3 2 1 - 1 1 - 4 8 x 10 - bit - - v - lqfp 48 nuc1 2 3lc2 an 1 36 12 4 up to 36 4 x 32 - bit 2 3 2 1 - 1 1 - 4 8 x 10 - bit - - v - lqfp 48 nuc1 2 3sd4 an 0 6 8 20 4 up to 47 4 x 32 - bit 2 3 2 1 - 1 1 - 4 8 x 10 - bit - - v - lqfp64 nuc1 2 3sc2 an 1 36 12 4 up to 47 4 x 32 - bit 2 3 2 1 - 1 1 - 4 8 x 10 - bit - - v - lqfp64 4.2.2 numicro ? nuc12 3 xxxaex selection guide part number flash (kb) sram (kb) isp rom (kb) i/o timer connectivity i 2 s comp. pwm adc rtc ebi isp \ icp \ iap 1.8v power pin package uart spi i 2 c usb lin ps/2 nuc1 2 3zd4 ae 0 68 20 4 up to 20 4 x 32 - bit 1 3 1 1 - - 1 - 3 3 x 10 - bit - - v - qfn33 nuc1 2 3zc2 ae 1 36 12 4 up to 20 4 x 32 - bit 1 3 1 1 - - 1 - 3 3 x 10 - bit - - v - qfn33 nuc1 2 3ld4 ae 0 6 8 20 4 up to 36 4 x 32 - bit 2 3 2 1 - 1 1 - 4 8 x 10 - bit - - v - lqfp 48 nuc1 2 3lc2 ae 1 36 12 4 up to 36 4 x 32 - bit 2 3 2 1 - 1 1 - 4 8 x 10 - bit - - v - lqfp 48 nuc1 2 3sd4 ae 0 6 8 20 4 up to 47 4 x 32 - bit 2 3 2 1 - 1 1 - 4 8 x 10 - bit - - v - lqfp64 nuc1 2 3sc2 ae 1 36 12 4 up to 47 4 x 32 - bit 2 3 2 1 - 1 1 - 4 8 x 10 - bit - - v - lqfp64
nuc123 may 3 , 201 7 page 16 of 99 rev. 2 . 0 4 nuc123 series datasheet numicro ? nuc 123 series pin configuration 4.3 4.3.1 numicro ? nuc123 xxxanx pin diagram numicro ? nuc123sxx an x lqfp 64 pin 4.3.1.1 figure 4 - 2 numicro ? nuc123sxx an x lqfp 64 - pin diagram s p i 2 _ s s 0 / a d c 0 / p d . 0 s p i 0 _ s s 1 / s p i 2 _ c l k / a d c 1 / p d . 1 i n t 0 / p b . 1 4 p b . 1 3 c l k o / s p i 1 _ s s 0 / p b . 1 2 s p i 1 _ m o s i 0 / p d . 8 p d . 9 c l k o / p d . 1 0 i n t 1 / p d . 1 1 s p i 1 _ s s 1 / s p i 2 _ s s 0 / u a r t 1 _ r x d / p b . 4 s p i 2 _ c l k / u a r t 1 _ t x d / p b . 5 s p i 2 _ m o s i 0 / u a r t 1 _ n r t s / p b . 6 s p i 2 _ m i s o 0 / u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s s p i 2 _ m i s o 1 / a d c 4 / p d . 4 s p i 2 _ m o s i 1 / a d c 5 / p d . 5 t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t t m 0 / p b . 8 a v d d i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 p a . 1 3 / p w m 1 p a . 1 4 / p w m 2 p a . 1 5 / p w m 3 / i 2 s _ m c l k / c l k o p c . 8 / s p i 1 _ s s 0 p c . 9 / s p i 1 _ c l k v s s v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 p b . 9 / s p i 1 _ s s 1 / t m 1 p b . 1 0 / s p i 0 _ s s 1 / t m 2 p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d n u c 1 2 3 s x x a n x l q f p 6 4 - p i n i 2 c 1 _ s c l / s p i 2 _ m o s i 0 / s p i 1 _ c l k / p a . 1 1 i 2 c 1 _ s d a / s p i 2 _ m i s o 0 / s p i 1 _ m i s o 0 / p a . 1 0 p c . 4 / s p i 0 _ m i s o 1 / u a r t 0 _ r x d p c . 5 / s p i 0 _ m o s i 1 / u a r t 0 _ t x d v s s v s s v d d p c . 1 2 / s p i 1 _ m i s o 1 / p w m 2 / i 2 s _ m c l k p c . 1 3 / s p i 1 _ m o s i 1 / p w m 3 / c l k o s p i 0 _ m i s o 1 / s p i 2 _ m i s o 0 / a d c 2 / p d . 2 s p i 0 _ m o s i 1 / s p i 2 _ m o s i 0 / a d c 3 / p d . 3 p s 2 _ d a t / i 2 c 0 _ s d a / a d c 6 / p f . 2 p s 2 _ c l k / i 2 c 0 _ s c l / a d c 7 / p f . 3
nuc123 may 3 , 201 7 page 17 of 99 rev. 2 . 0 4 nuc123 series datasheet numicro ? nuc12 3lxx an x lqfp 48 pin 4.3.1.2 figure 4 - 3 numicro ? nuc123lxx an x lqfp 48 - pin diagram p v s s a v d d 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n u c 1 2 3 l x x a n x l q f p 4 8 - p i n s p i 2 _ s s 0 / a d c 0 / p d . 0 s p i 0 _ s s 1 / s p i 2 _ c l k / a d c 1 / p d . 1 i n t 0 / p b . 1 4 t m 0 / p b . 8 s p i 1 _ s s 1 / s p i 2 _ s s 0 / u a r t 1 _ r x d / p b . 4 s p i 2 _ c l k / u a r t 1 _ t x d / p b . 5 s p i 2 _ m o s i 0 / u a r t 1 _ n r t s / p b . 6 s p i 2 _ m i s o 0 / u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s s p i 2 _ m i s o 1 / a d c 4 / p d . 4 s p i 2 _ m o s i 1 / a d c 5 / p d . 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 p a . 1 3 / p w m 1 p a . 1 4 / p w m 2 p a . 1 5 / p w m 3 / i 2 s _ m c l k / c l k o p c . 8 / s p i 1 _ s s 0 p c . 9 / s p i 1 _ c l k p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 p b . 9 / s p i 1 _ s s 1 / t m 1 p b . 1 0 / s p i 0 _ s s 1 / t m 2 i 2 c 1 _ s c l / s p i 2 _ m o s i 0 / s p i 1 _ c l k / p a . 1 1 i 2 c 1 _ s d a / s p i 2 _ m i s o 0 / s p i 1 _ m i s o 0 / p a . 1 0 p c . 4 / s p i 0 _ m i s o 1 / u a r t 0 _ r x d p c . 5 / s p i 0 _ m o s i 1 / u a r t 0 _ t x d p c . 1 2 / s p i 1 _ m i s o 1 / p w m 2 / i 2 s _ m c l k p c . 1 3 / s p i 1 _ m o s i 1 / p w m 3 / c l k o s p i 0 _ m i s o 1 / s p i 2 _ m i s o 0 / a d c 2 / p d . 2 s p i 0 _ m o s i 1 / s p i 2 _ m o s i 0 / a d c 3 / p d . 3 p s 2 _ d a t / i 2 c 0 _ s d a / a d c 6 / p f . 2 p s 2 _ c l k / i 2 c 0 _ s c l / a d c 7 / p f . 3
nuc123 may 3 , 201 7 page 18 of 99 rev. 2 . 0 4 nuc123 series datasheet numicro ? nuc12 3zxx an x qfn 33 pin 4.3.1.3 figure 4 - 4 numicro ? nuc123zxx an x qfn 33 - pin diagram n u c 1 2 3 z x x a n x q f n 3 3 - p i n 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 3 1 4 1 5 1 6 3 3 v s s a v d d s p i 0 _ s s 1 / s p i 2 _ c l k / a d c 1 / p d . 1 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t s p i 0 _ m i s o 1 / s p i 2 _ m i s o 0 / a d c 2 / p d . 2 s p i 0 _ m o s i 1 / s p i 2 _ m o s i 0 / a d c 3 / p d . 3 p v s s i n t 0 / p b . 1 4 s p i 1 _ s s 1 / s p i 2 _ s s 0 / u a r t 1 _ r x d / p b . 4 s p i 2 _ c l k / u a r t 1 _ t x d / p b . 5 l d o _ c a p v d d v s s i 2 c 1 _ s c l / s p i 2 _ m o s i 0 / s p i 1 _ c l k / p a . 1 1 i 2 c 1 _ s d a / s p i 2 _ m i s o 0 / s p i 1 _ m i s o 0 / p a . 1 0 p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s i c e _ c l k i c e _ d a t p c . 8 / s p i 1 _ s s 0 p c . 9 / s p i 1 _ c l k p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 p c . 1 2 / s p i 1 _ m i s o 1 / p w m 2 / i 2 s _ m c l k p c . 1 3 / s p i 1 _ m o s i 1 / p w m 3 / c l k o
nuc123 may 3 , 201 7 page 19 of 99 rev. 2 . 0 4 nuc123 series datasheet 4.3.2 numicro ? nuc12 3 xxxaex pin diagram numicro ? nuc12 3s xx a e x lqfp 64 pin 4.3.2.1 figure 4 - 5 numicro ? nuc12 3s xx a e x lqfp 64 - pin diagram s p i 2 _ s s 0 / a d c 0 / p d . 0 s p i 0 _ s s 1 / s p i 2 _ c l k / a d c 1 / p d . 1 i n t 0 / p b . 1 4 p b . 1 3 c l k o / s p i 1 _ s s 0 / p b . 1 2 s p i 1 _ m o s i 0 / p d . 8 p d . 9 c l k o / p d . 1 0 i n t 1 / p d . 1 1 s p i 1 _ s s 1 / s p i 2 _ s s 0 / u a r t 1 _ r x d / p b . 4 s p i 2 _ c l k / u a r t 1 _ t x d / p b . 5 s p i 2 _ m o s i 0 / u a r t 1 _ n r t s / p b . 6 s p i 2 _ m i s o 0 / u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s s p i 2 _ m i s o 1 / a d c 4 / p d . 4 s p i 2 _ m o s i 1 / a d c 5 / p d . 5 t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t t m 0 / p b . 8 a v d d i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 p a . 1 3 / p w m 1 p a . 1 4 / p w m 2 p a . 1 5 / p w m 3 / i 2 s _ m c l k / c l k o p c . 8 / s p i 1 _ s s 0 / p w m 0 p c . 9 / s p i 1 _ c l k v s s v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 p b . 9 / s p i 1 _ s s 1 / t m 1 / p w m 1 p b . 1 0 / s p i 0 _ s s 1 / t m 2 p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d n u c 1 2 3 s x x a e x l q f p 6 4 - p i n i 2 c 1 _ s c l / s p i 2 _ m o s i 0 / s p i 1 _ c l k / p a . 1 1 i 2 c 1 _ s d a / s p i 2 _ m i s o 0 / s p i 1 _ m i s o 0 / p a . 1 0 p c . 4 / s p i 0 _ m i s o 1 / u a r t 0 _ r x d p c . 5 / s p i 0 _ m o s i 1 / u a r t 0 _ t x d v s s v s s v d d p c . 1 2 / s p i 1 _ m i s o 1 / p w m 2 / i 2 s _ m c l k p c . 1 3 / s p i 1 _ m o s i 1 / p w m 3 / c l k o s p i 0 _ m i s o 1 / s p i 2 _ m i s o 0 / a d c 2 / p d . 2 s p i 0 _ m o s i 1 / s p i 2 _ m o s i 0 / a d c 3 / p d . 3 p s 2 _ d a t / i 2 c 0 _ s d a / a d c 6 / p f . 2 p s 2 _ c l k / i 2 c 0 _ s c l / a d c 7 / p f . 3
nuc123 may 3 , 201 7 page 20 of 99 rev. 2 . 0 4 nuc123 series datasheet numicro ? nuc12 3l xx a e x lqfp 48 pin 4.3.2.2 figure 4 - 6 numicro ? nuc12 3l xx a e x lqfp 48 - pin diagram p v s s a v d d 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n u c 1 2 3 l x x a e x l q f p 4 8 - p i n s p i 2 _ s s 0 / a d c 0 / p d . 0 s p i 0 _ s s 1 / s p i 2 _ c l k / a d c 1 / p d . 1 i n t 0 / p b . 1 4 t m 0 / p b . 8 s p i 1 _ s s 1 / s p i 2 _ s s 0 / u a r t 1 _ r x d / p b . 4 s p i 2 _ c l k / u a r t 1 _ t x d / p b . 5 s p i 2 _ m o s i 0 / u a r t 1 _ n r t s / p b . 6 s p i 2 _ m i s o 0 / u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s s p i 2 _ m i s o 1 / a d c 4 / p d . 4 s p i 2 _ m o s i 1 / a d c 5 / p d . 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 p a . 1 3 / p w m 1 p a . 1 4 / p w m 2 p a . 1 5 / p w m 3 / i 2 s _ m c l k / c l k o p c . 8 / s p i 1 _ s s 0 / p w m 0 p c . 9 / s p i 1 _ c l k p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 p b . 9 / s p i 1 _ s s 1 / t m 1 / p w m 1 p b . 1 0 / s p i 0 _ s s 1 / t m 2 i 2 c 1 _ s c l / s p i 2 _ m o s i 0 / s p i 1 _ c l k / p a . 1 1 i 2 c 1 _ s d a / s p i 2 _ m i s o 0 / s p i 1 _ m i s o 0 / p a . 1 0 p c . 4 / s p i 0 _ m i s o 1 / u a r t 0 _ r x d p c . 5 / s p i 0 _ m o s i 1 / u a r t 0 _ t x d p c . 1 2 / s p i 1 _ m i s o 1 / p w m 2 / i 2 s _ m c l k p c . 1 3 / s p i 1 _ m o s i 1 / p w m 3 / c l k o s p i 0 _ m i s o 1 / s p i 2 _ m i s o 0 / a d c 2 / p d . 2 s p i 0 _ m o s i 1 / s p i 2 _ m o s i 0 / a d c 3 / p d . 3 p s 2 _ d a t / i 2 c 0 _ s d a / a d c 6 / p f . 2 p s 2 _ c l k / i 2 c 0 _ s c l / a d c 7 / p f . 3
nuc123 may 3 , 201 7 page 21 of 99 rev. 2 . 0 4 nuc123 series datasheet numicro ? nuc12 3z xx a e x qfn 33 pin 4.3.2.3 figure 4 - 7 numicro ? nuc12 3z xx a e x qfn 33 - pin diagram n u c 1 2 3 z x x a e x q f n 3 3 - p i n 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 3 1 4 1 5 1 6 3 3 v s s a v d d s p i 0 _ s s 1 / s p i 2 _ c l k / a d c 1 / p d . 1 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t s p i 0 _ m i s o 1 / s p i 2 _ m i s o 0 / a d c 2 / p d . 2 s p i 0 _ m o s i 1 / s p i 2 _ m o s i 0 / a d c 3 / p d . 3 p v s s i n t 0 / p b . 1 4 s p i 1 _ s s 1 / s p i 2 _ s s 0 / u a r t 1 _ r x d / p b . 4 s p i 2 _ c l k / u a r t 1 _ t x d / p b . 5 l d o _ c a p v d d v s s i 2 c 1 _ s c l / s p i 2 _ m o s i 0 / s p i 1 _ c l k / p a . 1 1 i 2 c 1 _ s d a / s p i 2 _ m i s o 0 / s p i 1 _ m i s o 0 / p a . 1 0 p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s i c e _ c l k i c e _ d a t p c . 8 / s p i 1 _ s s 0 / p w m 0 p c . 9 / s p i 1 _ c l k p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 p c . 1 2 / s p i 1 _ m i s o 1 / p w m 2 / i 2 s _ m c l k p c . 1 3 / s p i 1 _ m o s i 1 / p w m 3 / c l k o
nuc123 may 3 , 201 7 page 22 of 99 rev. 2 . 0 4 nuc123 series datasheet pin description 4.4 4.4.1 numicro ? nuc1 2 3 pin description pin no pin name type description lqfp 64 - pin lqfp 48 - pin qfn 33 - pin 1 3 1 pb.14 i/o digital gpio pin int0 i external interrupt 0 input pin 2 pb.13 i/o digital gpio pin 3 pb.12 i/o digital gpio pin spi 1_ ss0 i/o spi1 1 st slave select pin clko o frequency divider output pin 4 4 2 pa.11 i/o digital gpio pin spi 1_clk i/o spi1 serial clock pin spi2_ mosi0 i/o spi2 1 st mosi (master out, slave in) pin i2c1 _ scl i/o i 2 c1 clock pin 5* 5* 3* pa.10 i/o digital gpio pin spi1_miso 0 i/o spi1 1 st miso (master in, slave out) pin spi2_miso 0 i/o spi2 1 st miso (master in, slave out) pin i2c1 _ sda i/o i 2 c1 data input/output pin 6 pd.8 i/o digital gpio pin spi1_mosi 0 i/o spi1 1 st mosi (master out, slave in) pin 7 pd.9 i/o digital gpio pin 8 pd.10 i/o digital gpio pin clko o frequency divider output pin 9 pd.11 i/o digital gpio pin int1 i external interrupt 1 input pin 10 6 4 pb.4 i/o digital gpio pin uart1_rxd i uart1 data receiver input pin spi 2_ ss0 i/o spi2 1 st slave select pin spi 1_ss1 i/o spi1 2 nd slave select pin 11 7 5 pb.5 i/o digital gpio pin uart1_txd o uart1 data transmitter output pin spi 2_clk i/o spi2 serial clock pin 12 8 pb.6 i/o digital gpio pin uart1_nrts o uart1 request to send output pin
nuc123 may 3 , 201 7 page 23 of 99 rev. 2 . 0 4 nuc123 series datasheet spi2_mosi 0 i/o spi2 1 st mosi (master out, slave in) pin 13 9 pb.7 i/o digital gpio pin uart1_ncts i uart1 clear to send input pin spi2_miso 0 i/o spi2 1 st miso (master in, slave out) pin 14 10 6 ldo _cap p ldo output pin 15 11 7 v dd p power supply for i/o ports and ldo source for internal pll and digital function . voltage range is 2.5v ~ 5v. 16 12 8 v ss p ground 17 13 9 usb_ vbus usb power supply from usb host or hub 18 14 10 usb_ vdd33 _cap usb internal power regulator output 3.3v decoupling pin 19 15 11 usb_ d - usb usb differential signal d - 20 16 12 usb_ d+ usb usb differential signal d+ 21 pb.0 i/o digital gpio pin uart0_ rxd i uart 0 data receiver input pin 22 pb.1 i/o digital gpio pin uart0_txd o uart 0 data transmitter output pin 23 pb.2 i/o digital gpio pin uart0_nrts o uart 0 request to send output pin t m 2 _ ex t i timer2 external capture input pin 24 pb.3 i/o digital gpio pin uart0_ncts i uart 0 clear to send input pin t m 3 _ ex t i timer 3 external capture input pin 25 17 pc.5 i/o digital gpio pin spi0_mosi 1 i/o spi0 2 nd mosi (master out, slave in) pin uart0_txd o uart0 data transmitter output pin 26 18 pc.4 i/o digital gpio pin spi0_miso 1 i/o spi0 2 nd miso (master in, slave out) pin uart0_rxd i uart0 data receiver input pin 27 19 13 pc.3 i/o digital gpio pin spi0_mosi0 i/o spi0 1 st mosi (master out, slave in) pin i2s_ do o i 2 s data output pin 28 20 14 pc.2 i/o digital gpio pin spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin i2s_ di i i 2 s data input pin 29 21 15 pc.1 i/o digital gpio pin spi 0_clk i/o spi0 serial clock pin
nuc123 may 3 , 201 7 page 24 of 99 rev. 2 . 0 4 nuc123 series datasheet i2s_ bclk i/o i 2 s bit clock pin 30 22 16 pc.0 i/o digital gpio pin spi 0_ss0 i/o spi0 1 st slave select pin i2s _ lrclk i/o i 2 s left/right channel clock pin 31 23 pb.10 i/o digital gpio pin spi 0_ss 1 i/o spi0 2 nd slave select pin tm2 i/o timer2 event counter input / toggle output pin 32 24 pb.9 i/o digital gpio pin spi 1_ss1 i/o spi1 2 nd slave select pin tm1 i/o timer1 event counter input / toggle output pin pwm1 i/o pwm1 pwm output / capture input pin (nuc123xxxaex only) 33 v ss p ground 34 25 17 pc.13 i/o digital gpio pin spi1_mosi1 i/o spi1 2 nd mosi (master out, slave in) pin pwm3 i/o pwm3 pwm output / capture input pin clko o frequency divider output pin 35 26 18 pc.12 i/o digital gpio pin spi1_miso1 i/o spi1 2 nd miso (master in, slave out) pin pwm2 i/o pwm2 pwm output / capture input pin i2s _ mclk o i 2 s master clock output pin 36 27 19 pc.11 i/o digital gpio pin spi1_mosi 0 i/o spi1 1 st mosi (master out, slave in) pin 37 28 20 pc.10 i/o digital gpio pin spi1_miso 0 i/o spi1 1 st miso (master in, slave out) pin 38 v dd p power supply for i/o ports and ldo source for internal pll and digital function . voltage range is 2.5v ~ 5v. 39 29 21 pc.9 i/o digital gpio pin spi 1_clk i/o spi1 serial clock pin 40 30 22 pc.8 i/o digital gpio pin spi 1_ss 0 i/o spi1 1 st slave select pin pwm0 i/o pwm0 pwm output / capture input pin (nuc123xxxaex only) 41 31 pa.15 i/o digital gpio pin pwm3 i/o pwm3 pwm output / capture input pin i2s _ mclk o i 2 s master clock output pin clko o frequency divider output pin
nuc123 may 3 , 201 7 page 25 of 99 rev. 2 . 0 4 nuc123 series datasheet 42 v ss p ground 43 32 pa.14 i/o digital gpio pin pwm2 i/o pwm2 pwm output / capture input pin 44 33 pa.13 i/o digital gpio pin pwm1 i/o pwm1 pwm output / capture input pin 45 34 pa.12 i/o digital gpio pin pwm0 i/o pwm0 pwm output / capture input pin 46 35 23 ice_dat i/o serial w ired d ebugger d ata pin 47 36 24 ice_c l k i serial wired debugger clock input pin 48 37 25 av dd ap power supply for internal analog circuit 49 38 pd.0 i/o digital gpio pin adc0 ai adc channel 0 analog input pin spi 2_ss 0 i/o spi2 1 st slave select pin 50 39 26 pd.1 i/o digital gpio pin spi2_clk i/o spi2 serial clock pin spi0_ss1 i/o spi0 2 nd slave select pin adc1 ai adc channel 1 analog input pin 51 40 27 pd.2 i/o digital gpio pin spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin spi0_miso1 i/o spi0 2 nd miso (master in, slave out) pin adc2 ai adc channel 2 analog input pin 52 41 28 pd.3 i/o digital gpio pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin spi0_mosi1 i/o spi0 2 nd mosi (master out, slave in) pin adc3 ai adc channel 3 analog input pin 53 42 pd.4 i/o digital gpio pin adc4 ai adc channel 4 analog input pin spi2_ miso1 i/o spi2 2 nd miso (master in, slave out) pin 54 43 pd.5 i/o digital gpio pin adc5 ai adc channel 5 analog input pin spi2_mosi1 i/o spi2 2 nd mosi (master out, slave in) pin 55 pb.15 i/o digital gpio pin int1 i external interrupt 1 input pin tm0_ext i timer0 external capture input pin 56 44 29 pf.0 i/o digital gpio pin
nuc123 may 3 , 201 7 page 26 of 99 rev. 2 . 0 4 nuc123 series datasheet xt1_out o external 4~24 mhz high speed crystal output pin 57 45 30 pf.1 i/o digital gpio pin xt1_in i external 4~24 mhz high speed crystal input pin 58 46 31 nreset i external reset input: low active, set this pin low reset chip to initial state. with internal pull - up. 59 v ss p ground 60 v dd p power supply for i/o ports and ldo source for internal pll and digital circuit . voltage range is 2.5 v ~ 5v. 61 47 pf.2 i/o digital gpio pin adc6 ai adc channel 6 analog input pin i2c0_sda i/o i 2 c0 data input/output pin ps2_dat i/o ps/2 data pin 62 48 pf.3 i/o digital gpio pin adc7 ai adc channel 7 analog input pin i2c0_s cl i/o i 2 c0 clock pin ps2_clk i/o ps/2 clock pin 63 1 32 pv ss p pll ground 64 2 pb.8 i/o digital gpio pin tm0 i/o timer 0 event counter input / toggle output pin note: pin type i = digital input, o = digital output; ai = analog input; p = power pin; ap = analog power
nuc123 may 3 , 201 7 page 27 of 99 rev. 2 . 0 4 nuc123 series datasheet 5 block diagram numicro ? nuc123 block diagram 5.1 figure 5 - 1 numicro ? nuc12 3 block diagram a r m c o r t e x - m 0 7 2 m h z m e m o r y p d m a a p r o m & d a t a f l a s h 3 6 / 6 8 k b l d r o m 4 k b s r a m 1 2 / 2 0 k b t i m e r / p w m a n a l o g i n t e r f a c e 3 2 - b i t t i m e r x 4 w a t c h d o g t i m e r p w m / c a p t u r e t i m e r x 4 w i n d o w e d w a t c h d o g t i m e r 1 0 - b i t a d c x 8 c l o c k c o n t r o l l d o p o w e r o n r e s e t l v r b r o w n o u t d e t e c t i o n h i g h s p e e d o s c i l l a t o r 2 2 . 1 1 8 4 m h z h i g h s p e e d c r y s t a l 4 ~ 2 4 m h z l o w s p e e d o s c i l l a t o r 1 0 k h z p l l c o n n e c t i v i t y u a r t x 2 s p i x 3 i 2 c x 2 p s / 2 i 2 s u s b i / o p o r t s g e n e r a l p u r p o s e i / o r e s e t p i n e x t e r n a l i n t e r r u p t a h b / a p b b u s
nuc123 may 3 , 201 7 page 28 of 99 rev. 2 . 0 4 nuc123 series datasheet 6 functional d escription arm ? cortex ? - m0 core 6.1 the cort ex ? - m0 processor , a configurable, multistage, 32 - bit r isc processor , has an amba ah b - lite interface and includes an nvic component. the processor has optional hardware debug functionality , can execute thumb code , and is compatible with other c ortex ? - m profile processor s . the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an ex ception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an exception return. figure 6 - 1 shows the functional controller of processor. figure 6 - 1 functional controller diagram t he implemented device provides: ? a low gate count processor: C armv6 - m thumb? instruction set C thumb - 2 technology C armv6 - m compliant 24 - bit systick timer C a 32 - bit hardware multiplier C s ystem interface suppo rt ing little - endian data accesses C a b ility to have deterministic, fi xed - latency, interrupt handling C load/store - multiples and multicycle - multipli es abandoned and restarted to faci litate rapid interrupt handling C c application binary interface compliant exception model , which is the armv6 - m, c application binary interface (c - abi) compliant exception model that enables the use of pure c functions as interrupt handlers C low power sleep mode entry using wait for interrupt (wfi), wait for even t (wfe) instructions, or the return from interrupt sleep - on - exit feature ? nvic : c o r t e x - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x - m 0 p r o c e s s o r c o r t e x - m 0 c o m p o n e n t s w a k e u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
nuc123 may 3 , 201 7 page 29 of 99 rev. 2 . 0 4 nuc123 series datasheet C 32 external interrupt inputs, each with four levels of priority C dedicated non - maskabl e interrupt (nmi) input C support s both level - sensitive and pulse - sensitive interrupt lines C supports wake - up interrupt controller (wic) with ultra - low power sleep mode ? d ebug support C four hardware breakpoints C two watchpoints C program counter sampling register (pcsr) for non - intrusive code profiling C single step and vector catch capabilities ? bus interfaces: C single 32 - bit amba - 3 ahb - lite system interface provid ing simple integration to all system peripherals and memory C single 32 - b it slave port support ing the dap (debug access port)
nuc123 may 3 , 201 7 page 30 of 99 rev. 2 . 0 4 nuc123 series datasheet system manager 6.2 6.2.1 overview the system manager provides the functions of system control, power modes, wake - up sources, reset sources, system memory map, product id and multi - function pin control. the following sections describe the functions for ? system reset ? system power architecture ? system memory map ? system management registers for part number id , chip reset and on - chip controllers reset, and multi - functional pin control ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control registers 6.2.2 system reset the system reset can be issued by one of the events listed below. these reset event flags can be read from rst s rc register to determine the reset source. hardware reset can reset chip through peripheral reset signals. software reset can trigger reset through control registers. ? hardware reset sources C power - on reset (por) C low level on the nreset pin C watchdog time - out reset and window watchdog reset (wdt/wwdt reset) C low voltage reset (lvr) C brown - out detector reset (bod reset) ? software reset sources C chip reset will reset whole chip by writing 1 to chiprst ( iprstc1[0] ) C mcu reset to reboot but keeping the booting setting from aprom or ldrom by writing 1 to sysresetreq ( aircr[2] ) C cpu reset for cortex ? - m 0 core only by writing 1 to cpurst ( iprstc1[1] ) power - o n reset or chip_rst (iprst 1 [0]) reset s the whole chip including all peripherals , external crystal circuit and bs (ispcon[1]) bit . sysresetreq ( aircr[2] ) reset s the whole chip including all peripherals , but does not reset external crystal circuit and bs (ispcon[1]) bit .
nuc123 may 3 , 201 7 page 31 of 99 rev. 2 . 0 4 nuc123 series datasheet figure 6 - 2 system reset resources there are a total of 8 reset sources in the numicro ? family. in general, cpu reset is used to reset cortex ? - m 0 only; the other re set sources will reset cortex ? - m 0 and all peripherals. however, there are small differences between ea ch reset source and they are listed in table 6 - 1 . reset sources register por n reset wdt lvr bod chip mcu cpu rstsrc bit 0 = 1 bit 1 = 1 bit 2 = 1 bit 3 = 1 bit 4 = 1 bit 0 = 1 bit 5 = 1 bit 7 = 1 chip _ rst (iprst c1 [0]) 0x0 - - - - - - - bod _ en (bodcr[0]) reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 reload from config0 - bod _ vl (bodcr[2:1]) bod _ rsten (bodcr[3]) xtl12m_en (pwrcon [0]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - wdt_en (apbclk[0]) 0x1 - 0x1 - - 0x1 - - hclk _ s (clksel0[2:0]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - l o w v o l t a g e r e s e t p o w e r - o n r e s e t b r o w n - o u t r e s e t r e s e t p u l s e w i d t h 3 . 2 m s w d t / w w d t r e s e t ~ 5 0 k o h m @ 5 v r e s e t p u l s e w i d t h 2 s y s t e m c l o c k s n r e s e t v d d a v d d c h i p r e s e t c h i p _ r s t ( i p r s t c 1 [ 0 ] ) c p u r e s e t c p u _ r s t ( i p r s t c 1 [ 1 ] ) m c u r e s e t s y s r e s e t r e q ( a i r c r [ 2 ] ) b o d _ r s t e n ( b o d c r [ 3 ] ) r e s e t p u l s e w i d t h 6 4 w d t c l o c k s g l i t c h f i l t e r 3 6 u s s o f t w a r e r e s e t l v r _ e n ( b o d c r [ 7 ] ) p o r _ d i s _ c o d e ( p o r c r [ 1 5 : 0 ] ) s y s t e m r e s e t
nuc123 may 3 , 201 7 page 32 of 99 rev. 2 . 0 4 nuc123 series datasheet wdt _ s (clksel1[1:0]) 0x3 0x3 - - - - - - xtl12m_stb (clkstatus[0]) 0x0 - - - - - - - pll _ stb (clkstatus[2]) 0x0 - - - - - - - osc10k _ stb (clkstatus[ 3 ]) 0x0 - - - - - - - osc22m _ stb (clkstatus[4]) 0x0 - - - - - - - clk_sw_fail (clkstatus[7]) 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - wte (w tcr [7]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 wtcr 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 - - wtcralt 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - wwdtrld 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - wwdtcr 0x3f0800 0x3f0800 0x3f0800 0x3f0800 0x3f0800 0x3f0800 - - wwdtsr 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - wwdtcvr 0x3f 0x3f 0x3f 0x3f 0x3f 0x3f - - bs (ispcon[1]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - - dfbadr reload from config1 reload from config1 reload from config1 reload from config1 reload from config1 reload from config1 - - cbs (ispsta[2:1)) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - - vecmap (ispsta[2 0 :9]) (nuc123xxxaex only) reload base on config0 reload base on config0 reload base on config0 reload base on config0 reload base on config0 reload base on config0 - - other peripheral registers reset value - fmc registers reset value note: - means that the value of register keeps original setting. table 6 - 1 reset value of registers nreset reset 6.2.2.1 the nreset reset means to generate a reset signal by pull ing low nreset pin , which is an asynchronous reset input pin and can be used to reset system at any time. when the nreset volt age is lower than 0.2 v dd and the state keeps longer than 36 us (glitch filter ), c hip will be
nuc123 may 3 , 201 7 page 33 of 99 rev. 2 . 0 4 nuc123 series datasheet reset. the nreset reset will control the chip in reset state until the nreset voltage rises above 0.7 v dd and the state keeps longer than 36 us ( glitch filter). the rsts_reset ( rstsrc [1]) will be set to 1 if the previous reset source is nreset reset. figure 6 - 3 shows the nreset reset waveform. figure 6 - 3 nreset reset waveform power - on reset (por) 6.2.2.2 the power - on reset (por) is used to generate a stable system reset signal and forces the system to be reset when p ower - on to avoid unexpected behavior of mcu. when applying the power to mcu, the por module will detect the rising voltage and generate reset signal to system until the voltage is ready for mcu operation. at por reset, the rsts_por ( rstsrc [0]) will be set to 1 to indicate there is a por reset event. the rsts_por ( rstsrc [0]) bit can be cleared by writing 1 to it . figure 6 - 4 shows the waveform of power - on reset . s s n r e s e t 0 . 2 v d d 0 . 7 v d d n r e s e t r e s e t s s 3 6 u s 3 6 u s v d d v p o r p o w e r o n r e s e t 0 . 1 v
nuc123 may 3 , 201 7 page 34 of 99 rev. 2 . 0 4 nuc123 series datasheet figure 6 - 4 power - on reset (por) waveform l ow voltage reset (lvr) 6.2.2.3 if the low voltage reset function is enabled by setting the low voltage reset enable bit lvr _ en (bodcr[7]) to 1, after 1 00us delay, lvr detection circuit will be stable and the lvr function will be active. then lvr function will detect av dd during system operation. when the av dd voltage is lower than v lvr and the state keeps longer than de - glitch time (16*hclk cycles) , c hip will be reset. the lvr reset will control the chip in reset state until the av dd voltage rises above v lvr and the state keeps longer than de - glitch time . the rsts_reset ( rstsrc [1]) will be set to 1 if the previous reset source is nreset reset. figure 6 - 5 shows the low voltage reset waveform . figure 6 - 5 low voltage reset waveform brown - out detector reset (bod reset) 6.2.2.4 if the brown - o ut detector (bod) function is enabled by setting the brown - o ut detector enable bit bod _ en ( bodcr [0]), brown - out detector function will detect av dd during system operation. when the av dd voltage is lower than v bod which is decided by bod _ en ( bodcr [0]) and bod _ vl (bodc r [2:1]) and the state keeps longer than de - glitch time (max(20*hclk cycles, 1*lirc cycle)) , c hip will be reset. the bod reset will control the chip in reset state until the av dd voltage rises above v bod and the state keeps longer than de - glitch time . the default value of bod _ en, bod _ vl and bod _ rsten is set by flash controller user configuration register cboden (config0[23]), cbov1 - 0 (config0[22:21]) and cborst (config0[20]) respectively. user can determine the initial bod setting by setting the config0 register . figure 6 - 6 shows the brown - out detector waveform . a v d d v l v r l o w v o l t a g e r e s e t t 1 ( < d e - g l i t c h t i m e ) t 2 ( = d e - g l i t c h t i m e ) t 3 ( = d e - g l i t c h t i m e ) l v r _ e n 1 0 0 u s d e l a y f o r l v r s t a b l e
nuc123 may 3 , 201 7 page 35 of 99 rev. 2 . 0 4 nuc123 series datasheet figure 6 - 6 brown - out detector waveform watch dog timer reset 6.2.2.5 in most industrial applications, system reliability is very important. to automatically recover the mcu from failure status is one way to improve system reliability. the watch dog timer (wdt) is widely used to check if the system works fine. if the mcu is crashed or out of control, it may cause the watch dog time - out. user may decide to enable system reset during watch dog time - out to recover the system and take action for the system crash/out - of - control after reset. software can check if the reset is caused by wa tch dog time - out to indicate the previous reset is a watch dog reset and handle the failure of mcu after watch dog time - out reset by checking rsts_wdt (rstsrc[2]). cpu reset, chip reset and mcu reset 6.2.2.6 the cpu reset means only cortex ? - m 0 core is reset and a ll other peripherals remain the same status after cpu reset. user can set the cpu reset cpu_rst (iprstc1[1]) to 1 to assert the cpu reset signal. the chip reset is same with power - on reset. the cpu and all peripherals are reset and bs (ispcon[1]) bit is au tomatically reloaded from config 0 setting. user can set the chip reset chip_rst (iprstc1[0]) to 1 to assert the chip reset signal. the mcu reset is similar with chip reset. the difference is that bs (ispcon[1]) will not be reloaded from config 0 setting and keep its original software setting for booting from aprom or ldrom. user can set the mcu reset sysresetreq(aircr[2]) to 1 to assert the mcu reset. a v d d v b o d l b o d o u t b o d r s t e n b r o w n - o u t r e s e t t 1 ( < d e - g l i t c h t i m e ) t 2 ( = d e - g l i t c h t i m e ) t 3 ( = d e - g l i t c h t i m e ) h y s t e r e s i s v b o d h
nuc123 may 3 , 201 7 page 36 of 99 rev. 2 . 0 4 nuc123 series datasheet 6.2.3 power modes and wake - up sources there are several wake - up sources in i dle mode and p ower - down mode. table 6 - 2 lists the available clocks for each power mode. power mode normal m ode idle m ode power - d own m ode definition cpu is in active state cpu is in sleep state cpu is in sleep state and all clocks stop except lirc. sram content retended. entry condition c hip is in normal mode after system reset released cpu executes wfi instruction. cpu sets sleep mode enable and power down enable and executes wfi instruction. wake - up sources n/a all interrupts wdt, i2c, timer, uart, bod and gpio available clocks all all except cpu clock lirc after wake - up n/a cpu back to normal mode cpu back to normal mode table 6 - 2 power mode difference table figure 6 - 7 power mode state machine n o r m a l m o d e c p u c l o c k o n h x t , h i r c , l i r c , h c l k , p c l k o n f l a s h o n p o w e r - d o w n m o d e c p u c l o c k o f f h x t , h i r c , h c l k , p c l k o f f f l a s h h a l t s y s t e m r e s e t r e l e a s e d c p u e x e c u t e s w f i i n t e r r u p t s o c c u r i d l e m o d e c p u c l o c k o f f h x t , h i r c , l i r c , h c l k , p c l k o n f l a s h h a l t 1 . s l e e p d e e p ( s c r [ 2 ] ) = 1 2 . p w r _ d o w n _ e n ( p w r c o n [ 7 ] ) = 1 p d _ w a i t _ c p u ( p w r c o n [ 8 ] ) = 1 3 . c p u e x e c u t e s w f i w a k e - u p e v e n t s o c c u r l i r c o n
nuc123 may 3 , 201 7 page 37 of 99 rev. 2 . 0 4 nuc123 series datasheet 1 . lirc (10 khz osc) on or off depend s on software setting in run mode . 2 . if timer clock source is selected as lirc and lirc is on. 3 . if wdt clock source is selected as lirc and lirc is on. normal mode idle mode power - d own mode hxt (4~20 mhz xtl) on on halt hirc (12 /16 mhz osc) on on halt lirc (10 khz osc) on on on/off 1 pll on on halt ldo on on on cpu on halt halt hclk/pclk on on halt sram retention on on on flash on on halt gpio on on halt pdma on on halt t i m e r on on on/off 2 pwm on on halt wdt on on on/off 3 wwdt on on halt uart on on halt ps/2 on on halt i 2 c on on halt spi on on halt i 2 s on on halt usb on on halt adc on on halt table 6 - 3 c lock s in power modes wake - up sources in p ower - down mode : wdt, i2c, timer, uart, bod , gpio and usb after chip enters power down, the following wake - up sources can wake chip up to n ormal mode . wake - up source wake - up condition system can enter power - down mode again condition * bod brown - out detector interrupt after software writes 1 to clear bod_intf (bodcr [ 4 ] ) . gpio gpio interrupt after software write 1 to clear the isrc[n] bit. timer timer interrupt after software writes 1 to clear twf ( tisr x [1]) and t i f ( tisr x [0]) .
nuc123 may 3 , 201 7 page 38 of 99 rev. 2 . 0 4 nuc123 series datasheet wdt wdt interrupt after software writes 1 to clear wtwkf ( wtcr [5]) (write protect). uart ncts wake - up a fter software writes 1 to clear dctsf ( ua_msr [ 0 ]) . i 2 c a ddressing i 2 c device after software writes 1 to clear wkupif (i2cwkupsts[0]). usb remote wake - up after software writes 1 to clear bus_sts ( usbd_intsts [0]). table 6 - 4 table 6 - 4 list s the condition about how to en ter p ow er - down mode again for each peripheral. *user needs to wait t his condition before setting pwr_down_en ( pwrcon [ 7 ]) and execute wfi to enter power - down mode . wake - up source wake - up condition system can enter power - down mode again condition * bod brown - out detector interrupt after software writes 1 to clear bod_intf (bodcr [ 4 ] ) . gpio gpio interrupt after software write 1 to clear the isrc[n] bit. timer timer interrupt after software writes 1 to clear twf ( tisr x [1]) and t i f ( tisr x [0]) . wdt wdt interrupt after software writes 1 to clear wtwkf ( wtcr [5]) (write protect). uart ncts wake - up a fter software writes 1 to clear dctsf ( ua_msr [ 0 ]) . i 2 c a ddressing i 2 c device after software writes 1 to clear wkupif (i2cwkupsts[0]). usb remote wake - up after software writes 1 to clear bus_sts ( usbd_intsts [0]). table 6 - 4 condition of entering power - down mode again
nuc123 may 3 , 201 7 page 39 of 99 rev. 2 . 0 4 nuc123 series datasheet 6.2.4 system power distribution in this chip , power distribution is divided into three segments : ? analog power from av dd and av ss provides the power for analog components operation. ? digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 1.8 v power for digital operation and i/o pins. ? usb transceiver power from vbus offers the power for operating the usb transceiver. the outputs of internal voltage regulators, ldo and usb_ vdd33 _cap , require an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same vo ltage level of the digital power (v dd ). figure 6 - 8 shows the power distribution of the numicro ? nuc123 series . figure 6 - 8 numicro ? nuc12 3 power distribution diagram v d d t o 1 . 8 v l d o u s b t r a n s c e i v e r 5 v t o 3 . 3 v l d o p l l 1 0 - b i t a d c b r o w n - o u t d e t e c t o r p o r 5 0 l o w v o l t a g e r e s e t f l a s h d i g i t a l l o g i c 3 . 3 v 1 . 8 v 2 2 . 1 1 8 4 m h z h i r c o s c i l l a t o r a v d d v d d v s s u s b _ v b u s u s b _ v d d 3 3 _ c a p u s b _ d + u s b _ d - l d o _ c a p 1 u f 1 u f i o c e l l g p i o p v s s n u c 1 2 3 p o w e r d i s t r i b u t i o n s r a m p o r 1 8 1 0 k h z l i r c o s c i l l a t o r
nuc123 may 3 , 201 7 page 40 of 99 rev. 2 . 0 4 nuc123 series datasheet 6.2.5 system memory map the numicro ? nuc123 series provides 4g - byte address ing space. the memory locations assigned to each on - chip controllers are shown in the table 6 - 5 . the detailed register definition, memory space, and programming detailed will be described in the following sections for each on - chip periph erals . the numicro ? nuc123 s eries only supports little - endian data format. address space token controllers flash and sram memory space 0x0000_0000 C 0x000 0 _ffff flash_ba flash memory space ( 64 kb ) 0x2000_0000 C 0x2000_ 4 fff sram_ba sram memory space ( 20 kb ) ahb controllers space (0x5000_0000 C 0x501f_ffff) 0x5000_0000 C 0x5000_01ff gcr_ba system global control registers 0x5000_0200 C 0x5000_02ff clk_ba clock control registers 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gpio_ba gpio control registers 0x5000_8000 C 0x5000_bfff pdma_ba peripheral dma control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers apb1 controllers space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 C 0x4000_7fff wdt_ba watchdog /window watchdog timer control registers 0x4001_0000 C 0x4001_3fff tmr0 1 _ba timer0 /timer1 control registers 0x4002_0000 C 0x4002_3fff i2c0_ba i 2 c0 interface control registers 0x4003_0000 C 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 C 0x4003_7fff spi 1 _ba spi 1 with master/slave function control registers 0x4004_0000 C 0x4004_3fff pwma_ba pwm0 /1/2/3 control registers 0x4005_0000 C 0x4005_3fff uart0_ba uart0 control registers 0x4006_0000 C 0x4006_3fff usbd_ba usb 2.0 fs device controller registers 0x400e_0000 C 0x400e_ffff adc_ba analog - digital - converter (adc) control registers apb2 controllers space (0x4010_0000 ~ 0x401f_ffff) 0x4010_0000 C 0x4010_3fff ps2_ba ps / 2 interface control registers 0x4011_0000 C 0x4011_3fff tmr2 3 _ba timer2 /timer3 control registers 0x4012_0000 C 0x4012_3fff i2c1_ba i 2 c1 interface control registers 0x4013_0000 C 0x4013_3fff spi 2 _ba spi 2 with master/slave function control r egisters 0x4015_0000 C 0x4015_3fff uart1_ba uart1 control registers 0x40 1 a_0000 C 0x40 1 a_3fff i2s_ba i 2 s interface control registers system controllers space (0x e000 _ e 000 ~ 0x e000 _ e fff) 0x e000 _ e 0 1 0 C 0x e000 _ e0 ff scs_ba system timer control registers
nuc123 may 3 , 201 7 page 41 of 99 rev. 2 . 0 4 nuc123 series datasheet 0x e000 _ e10 0 C 0x e000 _ ec ff scs_ba external interrupt controller control registers 0x e000 _ ed0 0 C 0x e000 _ ed8 f scs_ba system control registers table 6 - 5 address space assignments for on - chip controllers
nuc123 may 3 , 201 7 page 42 of 99 rev. 2 . 0 4 nuc123 series datasheet 6.2.6 system timer (systick) the cortex ? - m0 includes an integrated system timer, systick , which provides a simple, 24 - bit clear - on - write, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count down from the value in the systick current value register (syst_cvr) to zero, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock cycle , and then decrement on subsequent clocks. when the counter transitions to zero, the countflag status bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to zero before enabling the feature. this ensures the timer will count from the syst_rvr value rather than an arbitrary value when it is enabled. if the syst_rvr is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. this mechanism c an be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the arm ? cortex ? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
nuc123 may 3 , 201 7 page 43 of 99 rev. 2 . 0 4 nuc123 series datasheet 6.2.7 nested vectored interrupt controller (nvic) cortex ? - m0 provides an interrupt controller as an integral part of the exception mode, named as nested vectored interrupt controller (nvic). it is closely coupled to the processor kernel and provides following features: ? nested and vectored interr upt support ? automatic processor state saving and restoration ? dynamic priority changing ? reduced and deterministic interrupt latency the nvic prioritizes and handles all supported exceptions. all exceptions are handled in handler m ode . this nvic architecture supports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrup t to the current running ones priority. if the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. when any interrupts is accepted, the starting address of the interrupt service routin e (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlated isr by software. while the starting address is fetched, nvic will also automatically save proce ssor state including the registers pc, psr, lr, r0~r3, r12 to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interru pt request. the nvic supports tail chaining which handles back - to - back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic also supp orts late arrival which improves the efficiency of concurrent isrs. when a higher priority interrupt request occurs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the real - time capability. for more detailed information, please refer to the arm ? cortex ? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
nuc123 may 3 , 201 7 page 44 of 99 rev. 2 . 0 4 nuc123 series datasheet exception model and system interrupt map 6.2.7.1 table 6 - 6 lists the exception model supported by the numicro ? nuc1 23 series . software can set four levels of priority on some of these ex ceptions as well as on all interrupts. the highest user - configurable priority is denoted as 0 and the lowest priority is denoted as 3. the default priority of all the user - configurable interrupts is 0. note that priority 0 is treated as the fourth priority on the system, after three system exceptions reset, nmi and hard fault. exception name vector number priority reset 1 - 3 nmi 2 - 2 hard fault 3 - 1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 6 - 6 exception model vector number interrupt number ( bit i n interrupt registers ) interrupt name source ip interrupt d escription 0 ~ 15 - - - system exceptions 16 0 bod_out brown - out brown - out low voltage detected interrupt 17 1 wdt_int wdt watchdog /window watchdog timer interrupt 18 2 eint0 gpio external signal interrupt from pb.14 pin 19 3 eint1 gpio external signal interrupt from pb.15 or pd.11 pin 20 4 gpab_int gpio external signal interrupt from p a[15:0] / p b[1 3 : 0 ] 21 5 gpcd f _int gpio external interrupt from p c [15:0] / p d [15:0] / pf[3:0] 22 6 pwma_int pwm 0~3 pwm0 , pwm1, pwm2 and pwm 3 interrupt 23 7 reserved reserved reserved 24 8 tmr0_int tmr0 timer 0 interrupt 25 9 tmr1_int tmr1 timer 1 interrupt 26 10 tmr2_int tmr2 timer 2 interrupt 27 11 tmr3_int tmr3 timer 3 interrupt 28 12 uart0_int uart0 uart0 interrupt 29 13 uart1_int uart1 uart1 interrupt 30 14 spi0_int spi0 spi0 interrupt
nuc123 may 3 , 201 7 page 45 of 99 rev. 2 . 0 4 nuc123 series datasheet 31 15 spi1_int spi1 spi1 interrupt 32 16 spi2_int spi2 spi2 interrupt 33 17 reserved reserved reserved 34 18 i2c0_int i 2 c0 i 2 c0 interrupt 35 19 i2c1_int i 2 c1 i 2 c1 interrupt 36 20 reserved reserved reserved 37 21 reserved reserved reserved 38 22 reserved reserved reserved 39 23 usb_int usbd usb 2.0 fs device interrupt 40 24 ps2_int ps / 2 ps / 2 interrupt 41 25 reserved reserved reserved 42 26 pdma_int pdma pdma interrupt 43 27 i2s_int i 2 s i 2 s interrupt 44 28 pwrwu_int clkc clock controller interrupt for chip wake - up from power - down state 45 29 adc_int adc adc interrupt 46 30 reserved reserved reserved 47 31 reserved reserved reserved table 6 - 7 system interrupt map
nuc123 may 3 , 201 7 page 46 of 99 rev. 2 . 0 4 nuc123 series datasheet vector table 6.2.7.2 when any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. for armv6 - m, the vector table base address is fixed at 0x00000000. the vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. the vector number on previous page defines the order of entries in the vector table associated with exc eption handler entry as illustrated in previous section. vector table word offset description 0 sp_main C the main stack pointer vector number exception entry pointer using that vector number table 6 - 8 vector table format operation description 6.2.7.3 nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set - enable or interrupt clear - enable register bit - field. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current enabled state of the corresponding interrupts. when an interrupt is disabled, interrupt assertion will cause the interrupt to become pending ; however, the interrupt will not activate. if an interrupt is active when i t is disabled, it remains in its active state until cleared by reset or an exception return. clearing the enable bit prevents new activations of the associated interrupt. nvic interrupts can be pended/un - pended using a complementary pair of registers to th ose used to enable/disable the interrupts, named the set - pending register and clear - pending register respectively. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current pended state of the corresponding interrupts. the clear - pending register has no effect on the execution status of an active interrupt. nvic interrupts are prioritized by updating an 8 - bit field within a 32 - bit register (each register supporting four interrupts). the general registers associated with the nvic are all accessible from a block of memory in the system control space and will be described in next section.
nuc123 may 3 , 201 7 page 47 of 99 rev. 2 . 0 4 nuc123 series datasheet clock controller 6.3 6.3.1 overview the clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also implements the power control function with the individually clock on/off control, clock source selection and clock di vider. the chip enters power - down mode when cortex ? - m0 core executes the wfi instruction only if the pwr_down_en (pwrcon[7]) bit and pd_wait_cpu (pwrcon[8]) bit are both set to 1 . after that, chip enter s power - down mode and wait for wake - up interrupt sourc e triggered to leave power - down mode. in the power - down mode, the clock controller turns off the 4~24 mhz external high speed crystal oscillator and 22.1184 mhz internal high speed rc oscillator to reduce the overall system power consumption. the figure 6 - 9 and figure 6 - 10 show the clock generator and the overview of the clock source control. the clock gen erator consists of 4 clock sources as listed below: ? 4~24 mhz external high speed crystal oscillator (hxt) ? p rogrammable pll output clock frequency (pll fout) , pll source can be from 4~24 mhz external high speed crystal oscillator (hxt) or 22.1184 mhz internal high speed rc oscillator (hirc)) ? 22.1184 mhz i nternal high speed rc oscillator (hirc) ? 10 khz internal low speed rc oscillator (lirc) each of these clock sources has certain stable time to wait for clock operating at stable frequency. when clock source is enabled, a stable counter start counting and correlated clock stable index (osc22m_stb(clkstatus[4]), osc10k_stb(clkstatus[3]), pll_stb(clkstatus[2]) and xtl12m_stb(clkstatus[0])) are set to 1 after stable counter value reac h a define value as shown in table 6 - 9 . system and peripheral can use the clock as its operating clock only when correlate clock stable index is set to 1. the clock stable index will auto clear when user disables the clock source (osc10k_en(pwrcon[3]), osc22m_en(pwrcon[2]), xtl12m_en(pwrcon[0]) and pd(pllcon[16])). besides, the clock stable index of hxt, hirc and pll will auto clear when chip enter power - down and cloc k stable counter will re - counting after chip wake - up if correlate clock is enabled. clock source clock stable c ount v alue hxt 4096 hxt clock pll 6144 pll source (pll source is hxt if pll_src(pllcon[19]) = 0, or hirc if pll_src(pllcon[19]) = 1) hirc 256 hirc clock lirc 1 lirc table 6 - 9 clock stable count value table
nuc123 may 3 , 201 7 page 48 of 99 rev. 2 . 0 4 nuc123 series datasheet figure 6 - 9 clock generator global view diagram x t 1 _ i n 4 ~ 2 4 m h z h x t x t l 1 2 m _ e n ( p w r c o n [ 0 ] ) x t 1 _ o u t 2 2 . 1 1 8 4 m h z h i r c o s c 2 2 m _ e n ( p w r c o n [ 2 ] ) 0 1 p l l p l l _ s r c ( p l l c o n [ 1 9 ] ) p l l f o u t 1 0 k h z l i r c o s c 1 0 k _ e n ( p w r c o n [ 3 ] ) h x t h i r c l i r c l e g e n d : h x t = 4 ~ 2 4 m h z e x t e r n a l h i g h s p e e d c r y s t a l o s c i l l a t o r h i r c = 2 2 . 1 1 8 4 m h z i n t e r n a l h i g h s p e e d r c o s c i l l a t o r l i r c = 1 0 k h z i n t e r n a l l o w s p e e d r c o s c i l l a t o r n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
nuc123 may 3 , 201 7 page 49 of 99 rev. 2 . 0 4 nuc123 series datasheet figure 6 - 10 clock generator global view diagram h i r c ( 2 2 . 1 1 8 4 m h z ) h x t ( 4 ~ 1 2 m h z ) l i r c ( 1 0 k h z ) 1 1 1 0 1 1 0 1 0 p l l f o u t h x t l i r c h i r c 0 0 0 c l k s e l 0 [ 2 : 0 ] 1 / ( h c l k _ n + 1 ) p c l k 1 / ( a p b d i v + 1 ) c l k s e l 1 [ 2 2 : 2 0 ] c l k s e l 1 [ 1 8 : 1 6 ] c l k s e l 1 [ 1 4 : 1 2 ] c l k s e l 1 [ 1 0 : 8 ] 1 0 p l l h i r c h x t p l l c o n [ 1 9 ] 1 1 1 0 1 1 0 1 0 0 0 0 1 / 2 1 / 2 1 / 2 h c l k h i r c h x t c l k s e l 0 [ 5 : 3 ] 0 0 1 1 / 2 c p u c l k h c l k p l l f o u t 0 1 0 1 1 1 0 1 1 l i r c h i r c { c l k s e l 2 [ 8 ] , c l k s e l 1 [ 2 9 : 2 8 ] } 0 0 0 h c l k h x t { c l k s e l 2 [ 9 ] , c l k s e l 1 [ 3 1 : 3 0 ] } 1 0 1 1 h i r c 0 0 h c l k h x t c l k s e l 2 [ 3 : 2 ] 1 0 1 1 p l l f o u t h i r c 0 1 0 0 h c l k h x t c l k s e l 2 [ 1 : 0 ] h i r c 0 0 0 1 1 1 1 0 0 t m x , x = 0 , 1 , 2 h i r c l i r c h x t h c l k 0 1 0 0 1 1 1 0 1 1 l i r c h c l k c l k s e l 2 [ 1 7 : 1 6 ] 1 / 2 0 4 8 l i r c 1 0 1 1 l i r c h c l k c l k s e l 1 [ 1 : 0 ] 1 / 2 0 4 8 c l k s e l 1 [ 3 : 2 ] 1 / ( a d c _ n + 1 ) 1 / ( u s b _ n + 1 ) p l l f o u t 1 1 p l l f o u t h i r c 0 1 0 0 h x t c l k s e l 1 [ 2 5 : 2 4 ] 1 / ( u a r t _ n + 1 ) 1 0 h c l k p l l f o u t c l k s e l 1 [ 4 ] c l k s e l 1 [ 5 ] c l k s e l 1 [ 6 ] c p u a h b p d m a a p b i 2 c 0 - 1 t m r 0 t m r 1 t m r 2 t m r 3 b o d s y s t i c k p w m 2 - 3 p w m 0 - 1 p s 2 f m c f d i v i 2 s a d c u s b w d t w w d t u a r t 0 / 1 s p i 0 s p i 1 s p i 2 n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
nuc123 may 3 , 201 7 page 50 of 99 rev. 2 . 0 4 nuc123 series datasheet 6.3.2 system clock and systick clock the system clock has 5 clock sources which were generated from clock generator block. the clock source switch depends on the register hclk_ s ( clksel0[2:0]). the block diagram is show n in figure 6 - 11 . figure 6 - 11 system clock block diagram the clock source of systick in cortex ? - m0 core can use cpu clock or external clock (syst_csr[2]). if using external clock, the systick clock (stclk) has 4 clock sources. the clock source switch depends on the setting of the register stclk_s (clksel0[5:3] ) . the block diagram is shown in figure 6 - 12 . figure 6 - 12 systick c lock control block diagram 6.3.3 peripherals clock the peripherals clock had different clock source switch setting depend ing on different peripheral s . please refer to the clksel1 and clksel2 reg ister description in trm . 6.3.4 power - down m ode clock when chip enters into power - down mode, system clocks, some clock sources, and som e peripheral clocks will be disabled. some clock sources and peripherals clock are still active in power - down mode. the clocks kept active are list ed below: ? clock generator C internal 10 khz low speed oscillator clock 1 1 1 0 1 1 0 1 0 p l l f o u t h x t ( 4 ~ 2 4 m h z ) l i r c ( 1 0 k h z ) h i r c ( 2 2 . 1 1 8 4 m h z ) 0 0 0 1 / ( h c l k _ n + 1 ) p c l k 1 / ( a p b d i v + 1 ) 0 0 1 1 / 2 c p u c l k h c l k c p u i n p o w e r d o w n m o d e h c l k _ s ( c l k s e l 0 [ 2 : 0 ] ) c p u a h b a p b n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e . 1 1 1 0 1 1 0 1 0 0 0 0 1 / 2 1 / 2 1 / 2 h c l k s t c l k _ s ( c l k s e l 0 [ 5 : 3 ] ) s t c l k h i r c ( 2 2 . 1 1 8 4 m h z ) h x t ( 4 ~ 2 4 m h z ) n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
nuc123 may 3 , 201 7 page 51 of 99 rev. 2 . 0 4 nuc123 series datasheet ? wdt/timer /p wm peripherals clock ( w hen 10 khz intertnal low speed rc oscillator (lirc) is adopted as clock source) 6.3.5 frequency divider output this device is equipped with a power - of - 2 frequency divider which is composed by16 chained divide - by - 2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to clko function pin. therefore there are 16 options of power - of - 2 divided clocks with the frequency from f in /2 1 to f in /2 1 6 where fin is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4 - bit value in fse l ( frqdiv[3:0] ) . when writ ing 1 to divider_en (frqdiv[4]), the chained counter starts to count. when writ ing 0 to divider_en (frqdiv[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. figure 6 - 13 clock source of fr e quency divider figure 6 - 14 block diagram of frequency divider 1 0 1 1 0 0 h c l k f r q d i v _ s ( c l k s e l 2 [ 3 : 2 ] ) h i r c ( 2 2 . 1 1 8 4 m h z ) h x t ( 4 ~ 2 4 m h z ) f d i v _ e n ( a p b c l k [ 6 ] ) f r q d i v _ c l k n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e . 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 : : 1 6 t o 1 m u x 1 / 2 1 / 2 2 1 / 2 3 1 / 2 1 5 1 / 2 1 6 . . . f s e l ( f r q d i v [ 3 : 0 ] ) c l k o f r q d i v _ c l k 1 6 c h a i n e d d i v i d e - b y - 2 c o u n t e r d i v i d e r _ e n ( f r q d i v [ 4 ] ) e n a b l e d i v i d e - b y - 2 c o u n t e r
nuc123 may 3 , 201 7 page 52 of 99 rev. 2 . 0 4 nuc123 series datasheet flash memory controller (fmc) 6.4 6.4.1 overview the numicro ? nuc1 23 series is equipped with 68/36 kbytes on - chip embedded flash for application program memory (aprom) and data flash , and 4 kbytes for isp loader program memory (ldrom) that could be programmed boot loader to update aprom and data flash through in - system - programming (isp) procedure. the isp function enables user to update embedded flash when chip is soldered on pcb. after chip is powered on, cortex ? - m0 cpu fetches code from aprom or ldrom decided by boot select (cbs ( config0 [7:6]) . use r can also select to enable or disable in - application - programming (iap) function through boot select (cbs ( config0 [7:6]) . also , the nuc1 23 provides data flash for user, to store some application dependent data before chip is power ed off. 6.4.2 features ? run s up to 72 mhz and op tional up to 50mhz with zero wait state for continuous address read access ? supports 6 8 /3 6 k b application program rom (aprom) ? supports 4kb loader rom (ldrom) ? supports d ata f lash with configurable memory size ? supports 8 bytes user configuration block to control system initiation ? supports 512 bytes page erase for all embedded flash ? supports in - system - programm ing (isp) / in - application - program ming (iap) to update embedded flash memory
nuc123 may 3 , 201 7 page 53 of 99 rev. 2 . 0 4 nuc123 series datasheet general purpose i/o (gpio) 6.5 6.5.1 overview the numicro ? nuc 123 series has u p to 47 general purpose i/o pins shared with other function pins depend ing on the chip configuration. these 47 pins are arranged in 5 ports named gpioa, gpiob, gpioc, gpiod and gpio f . gpioa has 6 pins on pa[15:10]. gpiob has 15 pins on pb[15:12] and pb[10:0]. gpioc has 12 pins on pc[13:8] and pc[5:0]. gpiod has 10 pins on pd[11:8] and pd[5:0]. gpiof has 4 pins on pf[3:0]. each one of the 47 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be configured by software individually as input, output, open - drain or quasi - bidirectional mode. after the chip is reset, the i/o mode of all pins are depending on cioin i (c onfig 0[10]) ( nuc123xxxa e x only ) . each i/o pin has a very weakly individual pull - up resistor which is about 110 k ? ~300 k ? for v dd is from 5.0 v to 2.5 v. 6.5.2 features ? four i/o modes: C quasi bi - direction C push - pull output C open - drain output C input only with high impendence ? ttl/schmitt trigger input selectable by gpx_type[15:0] in gpx_mfp[31:16] ? i/o pin can be configured as interrupt source with edge/level setting ? supports high d river and h igh s ink i/o mode ? configu rable default i/o mode of all pins after reset by cioini ( config 0[10]) setting ( nuc123xxxa e x only ) C if cioin i (config[10]) is 0 , all gpio pins in input tri - state mode after chip reset C if cioin i (config[10]) is 1 , all gpio pins in quasi - bidirectional mode after chip reset ? i/o pin inter nal pull - up resistor enabled only in quasi - bidirectional i/o mode ? enabling th e pin interrupt function will also enable the wake - up function
nuc123 may 3 , 201 7 page 54 of 99 rev. 2 . 0 4 nuc123 series datasheet pdma controller (pdma) 6.6 6.6.1 overview the numicro ? nuc123 contains a six - channel peripheral direct memory access (pdma) controller and a cyclic redundancy check (crc) generator. the pdma can transfer data to and from memory or transfer data to and from apb devices. for pdma channel (pdma ch0~ch5), there is one - word buffer as transfer buffer between the peripherals apb devices and memory. the cpu can recognize the completion of a pdma operation by software polling or when it receives an internal pdma interrupt. the pdma controller can increase source or destination address o r fixed them as well. the p dma controller contains a cyclic redundancy check (crc) generator that can perform crc calculation with programmable polynomial settings. the crc engine supports cpu pio mode and p dma transfer mode. 6.6.2 features ? suppo rts six pdma cha nnels and one crc channel ; e ach pdma channel can support a unidirectional transfer ? amba ahb master/slave interface compatible, for data transfer and register read/write ? hardware round robin priority scheme . p dma channel 0 has the highest priority ? pdm a C per ipheral - to - memory, memory - to - peripheral, and memory - to - memory transfer C supports word/half - word/byte transfer data width from/to peripheral C supports address direction: increment, fixed C supports software , spi, uart, adc, pwm and i 2 s request ? cyclic redundancy check (crc) C supports four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 ? crc - ccitt: x 16 + x 12 + x 5 + 1 ? crc - 8: x 8 + x 2 + x + 1 ? crc - 16: x 16 + x 15 + x 2 + 1 ? crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 C programmable seed value C supports programmable order reverse setting for input data and crc checksum C supports programmable 1s complement setting for input data and crc checksum. C supports cpu pio mode or p dma transfer mode C supports 8/16/32 - bit of data width in cpu pio mode ? 8 - bit write mode: 1 - ahb clock cycle operation ? 16 - bit write mode: 2 - ahb clock cycle operation ? 32 - bit write mode: 4 - ahb clock cycle operation C supports byte alignment transfer length in crc p dma mode
nuc123 may 3 , 201 7 page 55 of 99 rev. 2 . 0 4 nuc123 series datasheet timer control ler (tmr) 6.7 6.7.1 overview the timer c ontroller includes four 32 - bit timers, t imer 0 ~ t imer 3, allowing user to easily implement a timer control for applications. the timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. 6.7.2 features ? four sets of 32 - bit timers with 24 - bit up counter and one 8 - bit prescale counter ? independent clock source for each timer ? provides one - shot, periodic, toggle - output and continuous counting operation modes ? 24 - bit up counter value is readable through tdr (td r[23:0] ) ? support s event counting function ? 24 - bit capture value is readable through t cap ( t cap[23:0] ) ? supports external capture pin event f or interval measurement ? supports external capture pin event to reset 24 - bit up counter ? supports chip wake - up fro m idle/power - down mode if a timer interrupt signal is generated
nuc123 may 3 , 201 7 page 56 of 99 rev. 2 . 0 4 nuc123 series datasheet pwm generator and capture timer (pwm) 6.8 6.8.1 overview the numicro ? nuc123 series has 1 set of pwm group support ing 1 set of pwm g enerators which can be configured as 4 independent pwm outputs, pwm0~pwm 3 , or as 2 complementary pwm pairs, (pwm0, pwm1), (pwm2, pwm3) with two programmable dead - zone generators. pwm output function can be altern ate d to c apture function. each pwm g enerator has one 8 - bit prescaler, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16 - bit pwm down - counters for pwm period control, two 16 - bit compa rators for pwm duty control and one dead - zone generator. the pwm g enerators provide four independent pwm interrupt flags which are set by hardware when the corresponding pwm period down counter reaches zero. each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured as one - shot mode to produce only one pwm cycle signal or auto - reload mode to output pwm waveform continuously. pwm can be use d to trigger adc when operati on in center - aligned mode. 6.8.2 features pwm function: ? up to 1 pwm group (pwma) to support 4 pwm channels or 2 pwm paired channels ? supports 8 - bit prescaler from 1 to 255 ? u p to 16 - bit resolution pwm timer ? pwm timer supports down and up - down operation type ? one - shot or auto - reload mode pwm ? pwm interrupt request synchronized with pwm period or duty ? supports dead - zone generator with 8 - bit resolution for 2 pwm paired channels ? supports trigger a dc on center point in center - aligned mode capture function: ? support s 4 capture input channels shared with 4 pwm output channels ? supports rising or falling capture condition ? supports rising or falling capture interrupt ? support s pdma transfer function for each channel
nuc123 may 3 , 201 7 page 57 of 99 rev. 2 . 0 4 nuc123 series datasheet watchdog timer (wdt) 6.9 6.9.1 overview the purpose of watchdog timer (wdt) is to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports the function to wake - up system from idle/power - down mode. 6.9.2 features ? 18 - bit free running up counter for wdt time - out interval ? selectable time - out interval (2 4 ~ 2 18 ) and the time - out interval is 1.6 ms ~ 26. 214 s if wdt_clk = 10 khz . ? system kept in reset state for a period of (1 / wdt_clk) * 63 ? supports selectable wdt reset delay period, including 1026 130 18 or 3 wdt_clk reset delay period ? supports to force wdt enabled after chip powered on or reset by setting cwdten in config0 register ? supports wdt time - out wake - up function only if wdt clock so urce is selected as 10 khz .
nuc123 may 3 , 201 7 page 58 of 99 rev. 2 . 0 4 nuc123 series datasheet window watchdog timer (wwdt) 6.10 6.10.1 overview the window watchdog timer is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. the 6 - bit down counter value will stop to update when chip is in idle or power - down mode. 6.10.2 features ? 6 - bit down counter value wwdtcval (wwdtcvr[5:0] ) and 6 - bit compare value wincmp (wwdtcr[21:16] ) to make the wwdt time - out window period flexible ? supports 4 - bit value p eriod sel (wwdtcr[11:8] ) to programmable maximum 11 - bit prescale counter period of wwdt counter
nuc123 may 3 , 201 7 page 59 of 99 rev. 2 . 0 4 nuc123 series datasheet uart interface controller (uart) 6.11 6.11.1 overview the numicro ? nuc123 series provide s two channels of universal asynchronous receiver/ transmitters (uart). uart control ler performs normal speed uart and support s flow control function. the uart controller performs a serial - to - parallel conversion on da ta received from the peripheral and a parallel - to - serial conversion on data transmitted from the cpu. each uart cont roller channel supports six types of interrupts. the uart c ontroller also supports irda si r and rs - 485 . 6.11.2 features ? full duplex, asynchronous communications ? separate s receive / transmit 16 /16 bytes entry fifo for data payloads ? support s hardware auto flow control/flow control ? programmable receiver buffer trigger level ? support s programmable baud - rate generator for each channel individually ? support s n cts wake - up function ? support s 8 - bit receiver buffer time - out detection function ? uart0/uart 1 served by the dma controller ? programmable transmitting data delay time between the last stop and the next start bit by setting dly ( ua_tor [ 15:8] ) ? support s break error, frame error, parity error and receive/transmit buffer overflow detect function ? fully programmable serial - interface characteristics C programmable number of data bit, 5 - , 6 - , 7 - , 8 - bit character C programmable parity bit, even, odd, no parity or stick parity bit generation and detection C programmable stop bit, 1, 1.5, or 2 stop bit generation ? support s irda sir function mode C support s for 3/16 - bit duration for normal mode ? support s rs - 485 function mode. C support s rs - 485 9 - bit mode C support s hardware or software direct enable to program n rts pin to control rs - 485 transmission direction
nuc123 may 3 , 201 7 page 60 of 99 rev. 2 . 0 4 nuc123 series datasheet ps/2 device controller (ps2d) 6.12 6.12.1 overview ps/2 device controller provides basic timing control for ps/2 communication. all communication between the device and the host is managed through the clk and data pins. unlike ps/2 keyboard or mouse device controller, the receiv ed/transmit code needs to be translated as meaningful code by firmware. the device controller generates the clk signal after receiving a request to send, but host has ultimate control over communication. data sent from the host to the device is read on the rising edge and data sent from device to the host is change after rising edge. a 16 bytes fifo is used to reduce cpu intervention. software can select 1 to 16 bytes for a continuous transmission. 6.12.2 features ? host communication inhibit and request to send detection ? reception frame error detection ? programmable 1 to 16 bytes transmit buffer to reduce cpu intervention ? double buffer for data reception ? s/w override bus
nuc123 may 3 , 201 7 page 61 of 99 rev. 2 . 0 4 nuc123 series datasheet i 2 c serial interface controller (master/slave) ( i 2 c ) 6.13 6.13.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt t o control the bus simultaneously. there are two sets of i 2 c controller s which support power - down wake - up function. 6.13.2 features ? supports up to two i 2 c ports ? master/sl ave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allow devices with different bit rates to communicate via one serial bu s ? built - in 14 - bit time - out counter requesting the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows. ? programmable cl ocks allow for versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition ( four slave address with mask option) ? supports power - dow n wake - up function
nuc123 may 3 , 201 7 page 62 of 99 rev. 2 . 0 4 nuc123 series datasheet serial peripheral interface (spi) 6.14 6.14.1 overview the serial peripheral interface (spi) applies to synchronous serial data communication and allows full duplex transfer . devices communicate in m aster/ slave mode with 4 - wire bi - direction interface. this numicro ? nuc123 series contain s up to three sets of spi controller s perform ing a serial - to - parallel conversion on data received from a peripheral device , and a parallel - to - serial conversion on data transmitted to a peripheral device . each set of spi controller can be configured as a m aster or a s lave device. this controller supports variable serial clock function for special application and it also supports 2 - b it t ransfer mode . the controller also supports pdma function to access the data buffer and also support s d ual i / o transfer mode . 6.14.2 features ? up to th ree sets of spi controller s ? support s m aster or slave mode operation ? support s 2 - b it t ransfer mode ? support s dual i / o transfer mode ? configurable bit length of a transfer word from 8 to 32 - bit ? provide separate 8 - layer depth transmit and receive fifo buffers ? support s msb first or lsb first transfer sequence ? up to t wo slave select lines in master mode ? support s b yte r eorder function ? support s configurable s uspend interval in master m ode ? variable output serial clock frequency in master mode ? support s pdma transfer ? support s 3 - wire , no slave select signal, bi - direction interfac e
nuc123 may 3 , 201 7 page 63 of 99 rev. 2 . 0 4 nuc123 series datasheet i 2 s controller (i 2 s) 6.15 6.15.1 overview the i 2 s controller consists of iis protocol to interface with external audio codec. two 8 word dep th fifo buffers for read path and write path respectively and is capable of handling 8 /16/24/ 32 bit s word sizes. p dma controller handle s the data movement between fifo and memo ry. 6.15.2 features ? operated as either m aster or s lave ? capable of handling 8, 16, 24 and 32 bit s word ? supports m on aural and stereo audio data ? supports four data format: C i 2 s data format C msb justified data format C pcm mode a C pcm mode b ? provides two 8 word depth fifo buffers, one for transmitting and the other for receiving ? generates interrupt requests when buffer levels cross a programmable boundary ? supports p dma transfer
nuc123 may 3 , 201 7 page 64 of 99 rev. 2 . 0 4 nuc123 series datasheet usb device controller (usb) 6.16 6.16.1 overview there is one set of usb 2.0 full - speed device controller and transceiver in this device . it is compliant with usb 2.0 full - speed device specification and support s c ontrol/ b ulk/ i nterrupt/ i sochronous transfer types. in this device controller, there are two main interfaces: apb bus and usb bus which comes from the usb phy transceiver. for the apb bus, the cpu can program control registers through it. there are 512 bytes internal sram as data buffer in this controller. for in or out transfer, it is necessary to write data to sram or read data from sram through the a pb interface or sie. user need s to set the effective starting address of sram for each endpoint buffer through buffer segmentation register (bufsegx). there are 8 endpoints in this controller. each of the endpoint can be configured as in or out endpoint. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. the block of endpoint control is also used to manage the data sequential synchronization, endpoint state control , current start address, transaction status, and data buffer status for each endpoint. there are four different interrupt events in this controller. they are the wake - up event , device plug - in or pl ug - out event, usb events, such as in ack, out ack, and bus events, such as suspend and resume, etc. any e vent will cause an interrupt, and user just need s to check the related event flags in interrupt event status register (usb_intsts) to acknowledge what kind of interrupt occurring, and then check the related usb endpoint status register (usb_epsts) to acknowledge what kind of event occurring in this endpoint . a software - disable function is also supported for this usb controller. it is used to simulate the disconnection of this device from the host. if user enables drv se0 bit (usb_drvse0), the usb controller will force the output of usb_d+ and usb_d - to level low and its function is disabled . after disable the drv se0 bit , host will enumerate th is usb device again. for more information on the universal serial bus , please refer to universal serial bus specification revision 1.1 . 6.16.2 features ? compliant with usb 2.0 full - speed specification ? provide s 1 interrupt vector with 4 different interrupt events (wakeup, fldet, usb and bus) ? support s control/bulk/interrupt/isochronous transfer type s ? support s suspend function when no bus activity existing for 3 ms ? provide s 8 endpoints for configurable control/bul k/interrupt/isochronous transfer types and maximum 512 bytes buffer size ? provide s remote wake - up capability
nuc123 may 3 , 201 7 page 65 of 99 rev. 2 . 0 4 nuc123 series datasheet analog - to - digital converter (adc) 6.17 6.17.1 overview numicro ? nuc123 series contain s one 1 0 - b i t successive approximation analog - to - digital converters (sar a/d converter) with 8 input channels. the a/d converter supports three operation modes: single, single - cycle scan and continuous scan mode. the a/d converters can be started by software , pwm center - aligned trigger and external stadc pin. 6.17.2 features ? conversio n range : 0 to av dd ? 1 0 - bit resolution and 8 - bit accuracy is guaranteed ? up to 8 single - end analog input channels ? maximum adc clock frequency as 6 mhz ( nuc123xxxa n x only ) ? maximum adc clock frequency as 3 mhz ( nuc123xxxa e x only ) ? up to 1 66 k sps (samples per second) conversion rate ( nuc123xxxa n x only ) ? up to 20 0 k sps (samples per second) conversion rate ( nuc123xxxa e x only ) ? three operating modes C single mode: a/d conversion is performed one time on a specified channel C single - cycle s can mode: a/d conversion is performed one cycle on all specified channels with the sequence from the lowest numbered channel to the highest numbered channel C continuous s can mode: a/d converter continuously performs single - cycle scan mode until software stops a/d convers ion ? a/d conversion started by : C software write s 1 to adst bit C external pin stadc (pb.8) C pwm center - aligned trigger ? supports 8 data registers to stored conversion result with valid and overrun indicators ? supports 2 sets of digital comparator s to monitor conversion result of spec ified channel and to generate an interrupt when conversion result matches comparison condition ? channel 7 supports 2 input sources: external analog voltage and internal band - gap voltag e ? support s pdma transfer
nuc123 may 3 , 201 7 page 66 of 99 rev. 2 . 0 4 nuc123 series datasheet 7 electrical character istics (nuc123xxxanx) absolute maximum ratings 7.1 symbol parameter min max unit v dd ? v ss dc power supply - 0.3 +7.0 v v in input voltage v ss - 0.3 v dd + 0.3 v 1/t clcl oscillator frequency 4 24 mhz t a operating temperature - 40 +85 t st storage temperature - 55 +150 i dd maximum current into v dd - 120 ma i ss maximum current out of v ss 120 ma i io maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond those listed under absolute maxim um ratings may adversely affect the lift and reliability of the device.
nuc123 may 3 , 201 7 page 67 of 99 rev. 2 . 0 4 nuc123 series datasheet dc electrical characteristics 7.2 ( v dd - v ss = 5 . 5 v, ta = 25 ? c) parameter sym specification s test conditions min typ max unit operation voltage v dd 2.5 5.5 v v dd = 2.5v ~ 5.5v up to 72 mhz v dd rise rate to ensure internal operation correctly v rise 0.05 v /ms power g round v ss av ss - 0.3 v ldo o utput v oltage v ldo 1.62 1 . 8 1.98 v v dd > 2. 5 v analog o perating v oltage av dd 0 v dd v when system use s analog function, please refer to chapter 7.4 for corresponding analog operating voltage operating c urrent normal run m ode at 72 mhz i dd1 36 ma v dd = 5.5v at 72 mhz, all ip and pll e nabled, xtal = 12 mhz i dd2 2 1 ma v dd = 5.5v at 72 mhz, all ip d isabled and pll e nabled, xtal = 12 mhz i dd3 35 ma v dd = 3v at 72 mhz, all ip and pll enabled, xtal = 12 mhz i dd4 2 0 ma v dd = 3v at 72 mhz, all ip d isabled and pll e nabled, xtal = 12 mhz operating c urrent normal run m ode at 12 mhz i dd5 7 ma v dd = 5.5v at 12 mhz, all ip e n a bled and pll d isabled, xtal = 12 mhz i dd6 4 ma v dd = 5.5v at 12 mhz, all ip and pll d isabled, xtal = 12 mhz i dd7 6 ma v dd = 3v at 12 mhz, all ip e nabled and pll d isabled, xtal = 12 mhz i dd8 3 ma v dd = 3v at 12 mhz, all ip and pll d isabled, xtal = 12 mhz operating c urrent normal run m ode i dd9 4 ma v dd = 5v at 4 mhz, all ip e nabled and pll d isabled, xtal = 4 mhz
nuc123 may 3 , 201 7 page 68 of 99 rev. 2 . 0 4 nuc123 series datasheet parameter sym specification s test conditions min typ max unit at 4 mhz i dd10 3 ma v dd = 5v at 4 mhz, all ip and pll d isabled, xtal = 4 mhz i dd11 4 ma v dd = 3v at 4 mhz, all ip e nabled and pll d isabled, xtal = 4 mhz i dd12 2 ma v dd = 3v at 4 mhz, all ip and pll d isabled, xtal = 4 mhz operating c urrent idle m ode at 72 mhz i idle1 29 ma v dd = 5.5v at 72 mhz, all ip and pll e nabled, xtal = 12 mhz i idle2 1 4 ma v dd = 5.5v at 72 mhz, all ip d isabled and pll e nabled, xtal = 12 mhz i idle3 28 ma v dd = 3v at 72 mhz, all ip and pll e nabled, xtal = 12 mhz i idle4 13 ma v dd = 3v at 72 mhz, all ip d isabled and pll e nabled, xtal=12 mhz operating c urrent idle m ode at 12 mhz i idle5 6 ma v dd = 5.5v at 12 mhz, all ip e nabled and pll d isabled, xtal = 12 mhz i idle6 3 ma v dd = 5.5v at 12 mhz, all ip and pll d isabled, xtal = 12 mhz i idle7 5 ma v dd = 3v at 12 mhz, all ip e n a bled and pll d isabled, xtal = 12 mhz i idle8 2 ma v dd = 3 v at 12 mhz, all ip and pll d isabled, xtal = 12 mhz operating c urrent idle m ode at 4 mhz i idle9 3 ma v dd = 5v at 4 mhz, all ip e n a bled and pll d isabled, xtal = 4 mhz i idle10 2 ma v dd = 5v at 4 mhz, all ip and pll d isabled, xtal = 4 mhz i idle11 2 ma v dd = 3v at 4 mhz, all ip e n a bled and pll d isabled, xtal = 4 mhz i idle12 1 ma v dd = 3v at 4 mhz, all ip and pll d isabled, xtal = 4 mhz
nuc123 may 3 , 201 7 page 69 of 99 rev. 2 . 0 4 nuc123 series datasheet parameter sym specification s test conditions min typ max unit operating c urrent idle m ode at 1 0 k hz i idle5 131 u a v dd = 5.5v at 1 0 k hz, all ip e nabled and pll d isabled, lirc 10 khz enabled i idle6 129 u a v dd = 5.5v at 1 0 k hz, all ip and pll d isabled, lirc 10 khz enabled i idle7 125 u a v dd = 3v at 1 0 k hz, all ip e n a bled and pll d isabled, lirc 10 khz enabled i idle8 124 u a v dd = 3 v at 1 0 k hz, all ip and pll d isabled, lirc 10 khz enabled s tandby c urrent power - down m ode i pwd1 12 ? a v dd = 5.5v, no load when bov function disable d i pwd 2 9 ? a v dd = 3. 3 v, no load when bov function disable d input current pa, pb, pc, pd, pe , pf (quasi - bidirectional mode) i in1 - 64 ? a v dd = 5.5v, v in = 0v or v in = v dd input current at /reset [1] i in2 - 55 - 45 - 30 ? a v dd = 3.3v, v in = 0.45v input leakage current pa, pb, pc, pd, pe , pf i lk - 2 - + 2 ? a v dd = 5.5v, 0 < v in < v dd logic 1 to 0 transition current pa~p f (quasi - bidirectional mode) i tl [3] - 65 0 - - 200 ? a v dd = 5.5v, v in < 2.0v input low voltage pa, pb, pc, pd, pe , pf (ttl input) v il1 - 0.3 - 0.8 v v dd = 4.5v - 0.3 - 0.6 v dd = 2.5v input high voltage pa, pb, pc, pd, pe , pf (ttl input) v ih1 2.0 - v dd +0.2 v v dd = 5.5v 1. 5 - v dd +0.2 v dd = 3.0v input low voltage pa, pb, pc, pd, pe , pf (schmitt input) v il2 - 0.5 - 0. 35 v dd v input high voltage pa, pb, pc, pd, pe , pf (schmitt input) v ih2 0. 6 5 v dd - v dd +0.5 v hysteresis voltage of pa~pe (schmitt input) v hy 0.2 v dd v input low voltage xt1 [*2] v il3 0 - 0.8 v v dd = 4.5v 0 - 0.4 v dd = 3.0v input high voltage xt1 [*2] v ih3 3.5 - v dd +0.2 v v dd = 5.5v 2.4 - v dd +0.2 v dd = 3.0v negative going threshold (schmitt input), /reset v ils - 0.5 - 0. 2 v dd v positive going threshold (schmitt input), /reset v ihs 0. 6 v dd - v dd +0.5 v
nuc123 may 3 , 201 7 page 70 of 99 rev. 2 . 0 4 nuc123 series datasheet parameter sym specification s test conditions min typ max unit source current pa, pb, pc, pd, pe , pf (quasi - bidirectional mode) i sr11 - 30 0 - 37 0 - 45 0 ? a v dd = 4.5v, v s = 2.4v i sr12 - 50 - 7 0 - 9 0 ? a v dd = 2.7v, v s = 2.2v i sr12 - 40 - 60 - 80 ? a v dd = 2.5v, v s = 2.0v source current pa, pb, pc, pd, pe , pf (push - pull mode) i sr21 - 20 - 24 - 28 ma v dd = 4.5v, v s = 2.4v i sr22 - 4 - 6 - 8 ma v dd = 2.7v, v s = 2.2v i sr22 - 3 - 5 - 7 ma v dd = 2.5v, v s = 2.0v sink current pa, pb, pc, pd, pe , pf (quasi - bidirectional and push - pull mode) i sk1 10 16 20 ma v dd = 4.5v, v s = 0.45v i sk1 7 10 13 ma v dd = 2.7v, v s = 0.45v i sk1 6 9 12 ma v dd = 2.5v, v s = 0.45v brown - out voltage with bov_vl [1:0] =00b v bo2. 2 2. 1 2. 2 2. 3 v brown - out voltage with bov_vl [1:0] =01b v bo2. 7 2.6 2.7 2.8 v brown - out voltage with bov_vl [1:0] =10b v bo3.8 3. 7 3. 8 3.9 v brown - out voltage with bov_vl [1:0] =11b v bo4.5 4. 4 4.5 4. 6 v hysteresis range of bod voltage v b h 30 - 1 5 0 mv v dd = 2.5v - 5.5v note s : 1. n reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. pins of pa, pb, pc, pd and pe can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd =5.5 v, 5he transition current reaches its maximum value when v in approximates to 2v .
nuc123 may 3 , 201 7 page 71 of 99 rev. 2 . 0 4 nuc123 series datasheet ac electrical characteristics 7.3 7.3.1 external 4~24 mhz high speed oscillator note: duty cycle is 50%. symbol parameter condition s min typ max unit t chcx clock high time 1 0 - - ns t clcx clock low time 1 0 - - ns t clch clock rise time 2 - 1 5 ns t chcl clock fall time 2 - 1 5 ns 7.3.2 external 4~24 mhz high speed crystal parameter condition s min typ max unit input clock frequency external crystal 4 12 24 mhz temperature - - 40 - 85 v dd - 2. 5 5 5.5 v typical crystal application circuits 7.3.2.1 crystal c1 c2 r 4 mhz ~ 24 mhz 10~ 20pf 10~ 20pf without figure 7 - 1 typical crystal application circuit t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l 0 . 3 v d d 0 . 7 v d d x t 1 _ i n x t 1 _ o u t c 1 r c 2
nuc123 may 3 , 201 7 page 72 of 99 rev. 2 . 0 4 nuc123 series datasheet 7.3.3 internal 22.1184 mhz high speed oscillator parameter condition s min typ max unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 22.1184 - mhz calibrated internal oscillator frequency +25 ; v dd =5 v - 1 - +1 % - 40 ~+85 ; v dd =2.5 v~5.5 v - 3 - +3 % operation current v dd =5 v - 500 - ua 7.3.4 internal 10 khz low s p eed oscillator parameter condition s min typ max unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 10 - khz calibrated internal oscillator frequency +25 ; v dd =5 v - 30 - +30 % - 40 ~+85 ; v dd =2.5 v~5.5 v - 50 - +50 % note: internal operation voltage comes from ldo.
nuc123 may 3 , 201 7 page 73 of 99 rev. 2 . 0 4 nuc123 series datasheet analog characteristics 7.4 7.4.1 1 0 - bit saradc specification s p arameter s ym s pecifications t est c onditions m in typ m ax u nit operating voltage av dd 2.7 5.5 v av dd = v dd operating current i adc 1.5 ma av dd = v dd = 5v, f sps = 150k resolution r adc 10 bit reference voltage v ref a v dd v v ref connected to a v dd in chip adc input voltage v in 0 a v dd v sampling rate f sps 150k hz v dd = 5v, adc clock = 6mhz free running conversion integral n on - l inearity error (inl) inl 1 lsb differential n on - l inearity error (dnl) dnl 1 lsb gain e rror e g 2 lsb offset e rror e offset 3 lsb absolute e rror e abs 4 lsb adc c lock f requency f adc 100k 6m hz v dd = 5v clock c ycle ad cyc 36 cycle
nuc123 may 3 , 201 7 page 74 of 99 rev. 2 . 0 4 nuc123 series datasheet 7.4.2 ldo and power m anagement specification s parameter min typ max unit note input voltage 2. 5 5 5.5 v v dd input voltage output voltage 1.62 1 . 8 1.98 v v dd > 2. 5 v temperature - 40 25 85 cbp - 1 - uf resr = 1? notes: 1. it is recommended that a 10uf or higher capacitor and a 100nf bypass capacitor are connected between v dd and the closest v ss pin of the device. 2. to ensur e power stability, a 1uf (cbp) or higher capacitor must be connected between ldo pin and the closest vss pin of the device. 7.4.3 low voltage reset specification s parameter condition s min typ max unit operation voltage - 1.7 - 5.5 v quiescent current v dd = 5.5 v - - 5 ua temperature - - 40 25 85 threshold voltage temperature = 25 1.7 2.0 2.3 v temperature = - 40 - 2.4 - v temperature = 85 - 1.6 - v hysteresis - 0 0 0 v
nuc123 may 3 , 201 7 page 75 of 99 rev. 2 . 0 4 nuc123 series datasheet 7.4.4 brown - out detector specification s parameter condition s min typ max unit operation voltage - 2.5 - 5.5 v quiescent current a v dd = 5.5 v - - 125 a temperature - - 40 25 85 brown - out voltage bov_vl [1:0] = 11 4.4 4.5 4.6 v bov_vl [1:0] = 10 3.7 3.8 3.9 v bov_vl [1:0] = 01 2.6 2.7 2.8 v bov_vl [1:0] = 00 2. 1 2. 2 2. 3 v hysteresis - 30 - 150 mv 7.4.5 power - on reset (5v) specification s parameter condition s min typ max unit temperature - - 40 25 85 reset voltage v+ - 2 - v quiescent current vin>reset voltage - 1 - na
nuc123 may 3 , 201 7 page 76 of 99 rev. 2 . 0 4 nuc123 series datasheet 7.4.6 usb phy specification s usb dc electrical characteristics 7.4.6.1 symbol parameter conditions min typ max unit v ih input high (driven) 2.0 v v il input low 0.8 v v di differential input sensitivity |padp - padm| 0.2 v v cm differential common - mode range includes v di range 0.8 2.5 v v se single - ended receiver threshold 0.8 2.0 v receiver hysteresis 200 mv v ol output low (driven) 0 0.3 v v oh output high (driven) 2.8 3.6 v v crs output signal cross voltage 1.3 2.0 v r pu pull - up resistor 1.425 1.575 k r pd pull - down resistor 14.25 15.75 k v trm termination voltage for upstream port pull up (rpu) 3.0 3.6 v z drv driver output resistance steady state drive* 10 c in transceiver capacitance pin to gnd 20 pf note: driver output resistance doesnt include series resistor resistance. usb full - speed driver electrical characteristics 7.4.6.2 symbol parameter conditions min typ max unit t fr ris ing t ime c l = 50p 4 20 ns t ff fall ing t ime c l = 50p 4 20 ns t frff ris ing and fall ing time matching t frff = t fr /t ff 90 111.11 % usb power dissipation 7.4.6.3 symbol parameter conditions min typ max unit i v bus v bus c urrent ( s teady s tate) standby 50 ua usb ldo specification 7.4.6.4 symbol parameter conditions min . typ . max . unit v bus vbus pin input voltage 4.0 5.0 5.5 v v dd33 ldo output voltage 3.0 3.3 3.6 v
nuc123 may 3 , 201 7 page 77 of 99 rev. 2 . 0 4 nuc123 series datasheet c bp external bypass capacitor 1.0 - uf flash dc electrical characteristics 7.5 symbol parameter conditions min. typ. max. unit v dd supply voltage 1.62 1.8 1.98 v [ 1 ] t ret data retention temp= 85 10 year t erase page erase time 20 ms t mer mass erase time 40 ms t prog program time 40 us i dd1 read current 0.25 ma i dd2 program/erase current 7 ma i pd power down current 1 20 ua note: v dd is source from chip ldo output voltage.
nuc123 may 3 , 201 7 page 78 of 99 rev. 2 . 0 4 nuc123 series datasheet spi dynamic characteristics 7.6 symbol parameter min typ max unit spi m aster mode (v dd = 4.5v ~ 5.5v, 30pf loading capacitor) t ds data setup time tbd tbd - ns t dh data hold time tbd - - ns t v data output valid time - tbd tbd ns spi m aster mode (v dd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time tbd tbd - ns t dh data hold time tbd - - ns t v data output valid time - tbd tbd ns spi slave mode (v dd = 4.5v ~ 5.5v, 30pf loading capacitor) t ds data setup time tbd - - ns t dh data hold time tbd - - ns t v data output valid time - tbd tbd ns spi slave mode (v dd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time tbd - - ns t dh data hold time tbd - - ns t v data output valid time - tbd tbd ns tbd: to be defined. figure 7 - 2 spi master d ynamic c haracteristics t iming c l k p = 0 , t x _ n e g = 1 , r x _ n e g = 0 o r c l k p = 1 , t x _ n e g = 0 , r x _ n e g = 1 c l k p = 0 , t x _ n e g = 0 , r x _ n e g = 1 o r c l k p = 1 , t x _ n e g = 1 , r x _ n e g = 0 m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d s p i c l k m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d c l k p = 0 c l k p = 1 t v t d s t d h t v t d s t d h
nuc123 may 3 , 201 7 page 79 of 99 rev. 2 . 0 4 nuc123 series datasheet figure 7 - 3 spi slave d ynamic c haracteristics t iming c l k p = 0 , t x _ n e g = 1 , r x _ n e g = 0 o r c l k p = 1 , t x _ n e g = 0 , r x _ n e g = 1 c l k p = 0 , t x _ n e g = 0 , r x _ n e g = 1 o r c l k p = 1 , t x _ n e g = 1 , r x _ n e g = 0 m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d s p i c l k m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d c l k p = 0 c l k p = 1 t v t d s t d h t v t d s t d h
nuc123 may 3 , 201 7 page 80 of 99 rev. 2 . 0 4 nuc123 series datasheet 8 electrical character istics (nuc123xxxaex) absolute maximum ratings 8.1 symbol parameter min max unit v dd ? v ss dc power supply - 0.3 +7.0 v v in input voltage v ss - 0.3 v dd + 0.3 v 1/t clcl oscillator frequency 4 24 mhz t a operating temperature - 40 +105 t st storage temperature - 55 +150 i dd maximum current into v dd - 120 ma i ss maximum current out of v ss 120 ma i io maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of the device.
nuc123 may 3 , 201 7 page 81 of 99 rev. 2 . 0 4 nuc123 series datasheet dc electrical characteristics 8.2 (v dd - v ss = 2 . 5 ~ 5.5 v, t a = 25 ? c) parameter sym specification s test conditions min typ max unit operation voltage v dd 2.5 5.5 v v dd = 2.5v ~ 5.5v up to 72 mhz v dd rise rate to ensure internal operation correctly v rise 0.05 v /ms power g round v ss av ss - 0.3 v ldo o utput v oltage v ldo 1.62 1.8 1.98 v v dd > 2. 5 v analog o perating v oltage av dd 0 v dd v operating c urrent normal run m ode at 72 mhz i dd1 39 ma v dd = 5.5v at 72 mhz, all ip and pll e nabled, xtal = 12 mhz i dd2 24 ma v dd = 5.5v at 72 mhz, all ip d isabled and pll e nabled, xtal = 12 mhz i dd3 37 ma v dd = 3v at 72 mhz, all ip and pll enabled, xtal = 12 mhz i dd4 23 ma v dd = 3v at 72 mhz, all ip d isabled and pll e nabled, xtal = 12 mhz operating c urrent normal run m ode at 12 mhz i dd5 10 ma v dd = 5.5v at 12 mhz, all ip e n a bled and pll d isabled, xtal = 12 mhz i dd6 7 ma v dd = 5.5v at 12 mhz, all ip and pll d isabled, xtal = 12 mhz i dd7 8 ma v dd = 3v at 12 mhz, all ip e nabled and pll d isabled, xtal = 12 mhz i dd8 6 ma v dd = 3v at 12 mhz, all ip and pll d isabled, xtal = 12 mhz operating c urrent normal run m ode i dd9 6 ma v dd = 5v at 4 mhz, all ip e nabled and pll d isabled, xtal = 4 mhz
nuc123 may 3 , 201 7 page 82 of 99 rev. 2 . 0 4 nuc123 series datasheet parameter sym specification s test conditions min typ max unit at 4 mhz i dd10 5 ma v dd = 5v at 4 mhz, all ip and pll d isabled, xtal = 4 mhz i dd11 4 ma v dd = 3v at 4 mhz, all ip e nabled and pll d isabled, xtal = 4 mhz i dd12 3 ma v dd = 3v at 4 mhz, all ip and pll d isabled, xtal = 4 mhz operating c urrent idle m ode at 72 mhz i idle1 28 ma v dd = 5.5v at 72 mhz, all ip and pll e nabled, xtal = 12 mhz i idle2 12 ma v dd = 5.5v at 72 mhz, all ip d isabled and pll e nabled, xtal = 12 mhz i idle3 25 ma v dd = 3v at 72 mhz, all ip and pll e nabled, xtal = 12 mhz i idle4 10 ma v dd = 3v at 72 mhz, all ip d isabled and pll e nabled, xtal=12 mhz operating c urrent idle m ode at 12 mhz i idle5 6 ma v dd = 5.5v at 12 mhz, all ip e nabled and pll d isabled, xtal = 12 mhz i idle6 3 ma v dd = 5.5v at 12 mhz, all ip and pll d isabled, xtal = 12 mhz i idle7 5 ma v dd = 3v at 12 mhz, all ip e n a bled and pll d isabled, xtal = 12 mhz i idle8 2 ma v dd = 3 v at 12 mhz, all ip and pll d isabled, xtal = 12 mhz operating c urrent idle m ode at 4 mhz i idle9 5 ma v dd = 5v at 4 mhz, all ip e n a bled and pll d isabled, xtal = 4 mhz i idle10 4 ma v dd = 5v at 4 mhz, all ip and pll d isabled, xtal = 4 mhz i idle11 3 ma v dd = 3v at 4 mhz, all ip e n a bled and pll d isabled, xtal = 4 mhz i idle12 2 ma v dd = 3v at 4 mhz, all ip and pll d isabled, xtal = 4 mhz
nuc123 may 3 , 201 7 page 83 of 99 rev. 2 . 0 4 nuc123 series datasheet parameter sym specification s test conditions min typ max unit operating c urrent idle m ode at 1 0 k hz i idle5 110 u a v dd = 5.5v at 1 0 k hz, all ip e nabled and pll d isabled, lirc 10 khz enabled i idle6 110 u a v dd = 5.5v at 1 0 k hz, all ip and pll d isabled, lirc 10 khz enabled i idle7 100 u a v dd = 3v at 1 0 k hz, all ip e n a bled and pll d isabled, lirc 10 khz enabled i idle8 100 u a v dd = 3 v at 1 0 k hz, all ip and pll d isabled, lirc 10 khz enabled standby c urrent power - down m ode i pwd1 15 ? a v dd = 5.5v, no load when bov function disable d i pwd 2 13 ? a v dd = 3. 3 v, no load when bov function disable d input current pa, pb, pc, pd, pe , pf (quasi - bidirectional mode) i in1 - 64 ? a v dd = 5.5v, v in = 0v input current at /reset [1] i in2 - 55 - 45 - 30 ? a v dd = 3.3v, v in = 0.45v input leakage current pa, pb, pc, pd, pe , pf i lk - 2 - + 2 ? a v dd = 5.5v, 0 < v in < v dd logic 1 to 0 transition current pa~p f (quasi - bidirectional mode) i tl [3] - 65 0 - - 200 ? a v dd = 5.5v, v in < 2.0v input low voltage pa, pb, pc, pd, pe , pf (ttl input) v il1 - 0.3 - 0.8 v v dd = 4.5v - 0.3 - 0.6 v dd = 2.5v input high voltage pa, pb, pc, pd, pe , pf (ttl input) v ih1 2.0 - v dd +0.2 v v dd = 5.5v 1. 5 - v dd +0.2 v dd = 3.0v input low voltage pa, pb, pc, pd, pe , pf (schmitt input) v il2 - 0.5 - 0. 35 v dd v input high voltage pa, pb, pc, pd, pe , pf (schmitt input) v ih2 0. 65 v dd - v dd +0.5 v hysteresis voltage of pa~pe (schmitt input) v hy 0.2 v dd v input low voltage xt1 [*2] v il3 0 - 0.8 v v dd = 4.5v 0 - 0.4 v dd = 3.0v input high voltage xt1 [*2] v ih3 3. 9 - v dd +0.2 v v dd = 5.5v 2.4 - v dd +0.2 v dd = 3.0v negative going threshold (schmitt input), /reset v ils - 0.5 - 0. 2 v dd v positive going threshold (schmitt input), /reset v ihs 0. 6 v dd - v dd +0.5 v
nuc123 may 3 , 201 7 page 84 of 99 rev. 2 . 0 4 nuc123 series datasheet parameter sym specification s test conditions min typ max unit source current pa, pb, pc, pd, pe , pf (quasi - bidirectional mode) i sr11 - 30 0 - 37 0 - 45 0 ? a v dd = 4.5v, v s = 2.4v i sr12 - 50 - 7 0 - 9 0 ? a v dd = 2.7v, v s = 2.2v i sr12 - 40 - 60 - 80 ? a v dd = 2.5v, v s = 2.0v source current pa, pb, pc, pd, pe , pf (push - pull mode) i sr21 - 2 4 - 2 8 - 32 ma v dd = 4.5v, v s = 2.4v i sr22 - 4 - 6 - 8 ma v dd = 2.7v, v s = 2.2v i sr22 - 3 - 5 - 7 ma v dd = 2.5v, v s = 2.0v sink current pa, pb, pc, pd, pe , pf (quasi - bidirectional and push - pull mode) i sk1 10 16 20 ma v dd = 4.5v, v s = 0.45v i sk1 7 10 13 ma v dd = 2.7v, v s = 0.45v i sk1 6 9 12 ma v dd = 2.5v, v s = 0.45v brown - out voltage with bov_vl [1:0] =00b v bo2. 2 2. 1 2. 2 2. 3 v brown - out voltage with bov_vl [1:0] =01b v bo2. 7 2.6 2.7 2.8 v brown - out voltage with bov_vl [1:0] =10b v bo3.8 3. 5 3. 7 3.9 v brown - out voltage with bov_vl [1:0] =11b v bo4.5 4. 2 4. 4 4. 6 v hysteresis range of bod voltage v b h 30 - 1 5 0 mv v dd = 2.5v - 5.5v note s : 1. n res e t pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. pins of p a , p b , p c , p d and p e can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd =5.5 v, 5he transition current reaches its maximum value when v in approximates to 2v.
nuc123 may 3 , 201 7 page 85 of 99 rev. 2 . 0 4 nuc123 series datasheet ac electrical characteristics 8.3 8.3.1 external 4~24 mhz high speed oscillator note: duty cycle is 50%. symbol parameter condition s min typ max unit t chcx clock high time 1 0 - - ns t clcx clock low time 1 0 - - ns t clch clock rise time 2 - 1 5 ns t chcl clock fall time 2 - 1 5 ns 8.3.2 external 4~24 mhz high speed crystal parameter condition s min typ max unit input clock frequency external crystal 4 - 24 mhz temperature - - 40 - 10 5 v dd - 2. 5 - 5.5 v typical crystal application circuits 8.3.2.1 crystal c1 c2 r 4 mhz ~ 24 mhz 10~20pf 10~20pf without figure 8 - 1 typical crystal application circuit t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l 0 . 3 v d d 0 . 7 v d d x t 1 _ i n x t 1 _ o u t c 1 r c 2
nuc123 may 3 , 201 7 page 86 of 99 rev. 2 . 0 4 nuc123 series datasheet 8.3.3 internal 22.1184 mhz high speed oscillator parameter condition s min typ max unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 22.1184 - mhz calibrated internal oscillator frequency +25 ; v dd =5 v - 1 - +1 % - 40 ~+ 10 5 ; v dd =2.5 v~5.5 v - 3 - +3 % operation current v dd =5 v - 500 - ua 8.3.4 internal 10 khz low speed oscillator parameter condition s min typ max unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 10 - khz calibrated internal oscillator frequency +25 ; v dd =5 v - 30 - +30 % - 40 ~+ 10 5 ; v dd =2.5 v~5.5 v - 50 - +50 % note: internal operation voltage comes fro m ldo.
nuc123 may 3 , 201 7 page 87 of 99 rev. 2 . 0 4 nuc123 series datasheet analog characteristics 8.4 8.4.1 1 0 - bit saradc specification s parameter sym . specification test conditions min. typ. max. unit operating voltage av dd 2.7 5.5 v av dd = v dd operating current i adc 1.5 ma av dd = v dd = 5v, f sps = 20 0k resolution r adc 10 bit reference voltage v ref av dd v v ref connected to av dd in chip adc input voltage v in 0 av dd v sampling rate f sps 200 k hz v dd = 5v, adc clock = 3 mhz free running conversion integral non - linearity error (inl) inl 1 lsb differential non - linearity (dnl) dnl 1 lsb gain error e g 2 lsb offset error e offset 3 lsb absolute error e abs 4 lsb adc clock frequency f adc 100 k 3 m hz v dd = 5v clock cycle ad cyc 1 6 cycle
nuc123 may 3 , 201 7 page 88 of 99 rev. 2 . 0 4 nuc123 series datasheet 8.4.2 ldo and power management specification s parameter min typ max unit note input voltage 2. 5 5 5.5 v v dd input voltage output voltage 1.62 1.8 1.98 v v dd > 2. 5 v temperature - 40 25 10 5 cbp - 1 - u f resr = 1 ? note s : 1. it is recommended that a 10uf or higher capacitor and a 100nf bypass capacitor are connected between v dd and the closest v ss pin of the device. 2. to ensur e power stability, a 1 uf (cbp) or higher capacitor must be connected between ldo pin and the closest v ss pin of the device. 8.4.3 low voltage reset specification s parameter condition s min typ max unit operation voltage - 1.7 - 5.5 v quiescent current v dd = 5.5 v - - 5 ua temperature - - 40 25 10 5 threshold voltage temperature = 25 1.7 2.0 2.3 v temperature = - 40 - 1.8 - v temperature = 85 - 2.2 - v hysteresis - 0 0 0 v
nuc123 may 3 , 201 7 page 89 of 99 rev. 2 . 0 4 nuc123 series datasheet 8.4.4 brown - out detector specification s parameter condition s min typ max unit operation voltage - 2.5 - 5.5 v quiescent current av dd = 5.5 v - - 125 a temperature - - 40 25 10 5 brown - out voltage bov_vl [1:0] = 11 4. 2 4. 4 4.6 v bov_vl [1:0] = 10 3. 5 3. 7 3.9 v bov_vl [1:0] = 01 2.6 2.7 2.8 v bov_vl [1:0] = 00 2. 1 2. 2 2. 3 v hysteresis - 30 - 150 m v 8.4.5 power - on reset (5v) specification s parameter condition s min typ max unit temperature - - 40 25 10 5 reset voltage v+ - 2 - v quiescent current vin>reset voltage - 1 - na
nuc123 may 3 , 201 7 page 90 of 99 rev. 2 . 0 4 nuc123 series datasheet 8.4.6 usb phy specification s usb dc electrical characteristics 8.4.6.1 symbol parameter conditions min typ max unit v ih input high (driven) 2.0 v v il input low 0.8 v v di differential input sensitivity |padp - padm| 0.2 v v cm differential common - mode range includes v di range 0.8 2.5 v v se single - ended receiver threshold 0.8 2.0 v receiver hysteresis 200 mv v ol output low (driven) 0 0.3 v v oh output high (driven) 2.8 3.6 v v crs output signal cross voltage 1.3 2.0 v r pu pull - up resistor 1.425 1.575 k r pd pull - down resistor 14.25 15.75 k v trm termination voltage for upstream port pull up (rpu) 3.0 3.6 v z drv driver output resistance steady state drive* 10 c in transceiver capacitance pin to gnd 20 pf note: driver output resistance doesnt include series resistor resistance. usb full - speed driver electrical characteristics 8.4.6.2 symbol parameter conditions min typ max unit t fr ris ing t ime c l = 50p 4 20 ns t ff fall ing t ime c l = 50p 4 20 ns t frff ris ing and fall ing time matching t frff = t fr /t ff 90 111.11 % usb power dissipation 8.4.6.3 symbol parameter conditions min typ max unit i v bus v bus c urrent ( s teady s tate ) standby 50 ua usb ldo specification 8.4.6.4 symbol parameter conditions min . typ . max . unit v bus vbus pin input voltage 4.0 5.0 5.5 v v dd33 ldo output voltage 3.0 3.3 3.6 v
nuc123 may 3 , 201 7 page 91 of 99 rev. 2 . 0 4 nuc123 series datasheet c bp external bypass capacitor 1.0 - uf
nuc123 may 3 , 201 7 page 92 of 99 rev. 2 . 0 4 nuc123 series datasheet flash dc electrical characteristics 8.5 symbol parameter conditions min . typ . max . unit v dd supply voltage 1.62 1.8 1.98 v [ 1 ] n endur endurance 2 0000 cycles [ 2 ] t ret data retention at 25 100 year t erase page erase time 20 ms t mer mass erase time 40 ms t prog program time 35 s i dd1 read current - tbd ma/mhz i dd2 program/erase current 7 ma i pd power down current - 1 20 a note1: v dd is source from chip ldo output voltage. note2: number of program/erase cycles. note3: this table is guaranteed by design, not test in production.
nuc123 may 3 , 201 7 page 93 of 99 rev. 2 . 0 4 nuc123 series datasheet spi dynamic characteristics 8.6 symbol parameter min typ max unit spi master mode (v dd = 4.5v ~ 5.5v, 30pf loading capacitor) t ds data setup time 4 2 - ns t dh data hold time 0 - - ns t v data output valid time - 7 11 ns spi master mode (v dd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time 5 3 - ns t dh data hold time 0 - - ns t v data output valid time - 13 18 ns spi slave mode (v dd = 4.5v ~ 5.5v, 30pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+4 - - ns t v data output valid time - 2*pclk+11 2*pclk+19 ns spi slave mode (v dd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+6 - - ns t v data output valid time - 2*pclk+19 2*pclk+25 ns figure 8 - 2 spi master dynamic characteristics ti min g c l k p = 0 , t x _ n e g = 1 , r x _ n e g = 0 o r c l k p = 1 , t x _ n e g = 0 , r x _ n e g = 1 c l k p = 0 , t x _ n e g = 0 , r x _ n e g = 1 o r c l k p = 1 , t x _ n e g = 1 , r x _ n e g = 0 m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d s p i c l k m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d c l k p = 0 c l k p = 1 t v t d s t d h t v t d s t d h
nuc123 may 3 , 201 7 page 94 of 99 rev. 2 . 0 4 nuc123 series datasheet figure 8 - 3 spi slave dynamic characteristics timing c l k p = 0 , t x _ n e g = 1 , r x _ n e g = 0 o r c l k p = 1 , t x _ n e g = 0 , r x _ n e g = 1 c l k p = 0 , t x _ n e g = 0 , r x _ n e g = 1 o r c l k p = 1 , t x _ n e g = 1 , r x _ n e g = 0 m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d s p i c l k m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d c l k p = 0 c l k p = 1 t v t d s t d h t v t d s t d h
nuc123 may 3 , 201 7 page 95 of 99 rev. 2 . 0 4 nuc123 series datasheet 9 package dimens i ons 64 l lqfp ( 7x7x1.4 mm footprint 2.0 mm ) 9.1
nuc123 may 3 , 201 7 page 96 of 99 rev. 2 . 0 4 nuc123 series datasheet 48 l lqfp ( 7x7x1.4 mm footprint 2.0 mm ) 9.2
nuc123 may 3 , 201 7 page 97 of 99 rev. 2 . 0 4 nuc123 series datasheet 33 l qfn ( 5x5x0.8 mm ) 9.3 1 8 8 9 16 1 16 17 17 9 24 24 32 25 25 32
nuc123 may 3 , 201 7 page 98 of 99 rev. 2 . 0 4 nuc123 series datasheet 10 revision h istory date revision description 201 2.04.01 1.0 0 preliminary v ersion . 2015. 05 . 29 2.00 1. merge d nuc123xxxanx & nuc123xxxaex into this document. 2015.11.04 2.01 1. removed adc function pin s of nuc123 qfn33 package type in section 4.3.1.3 , 4.3.2.3 and 4.4.1 . 2016.01.12 2.02 1. revised section 8.2 source current pa, pb, pc, pd, pe, pf (push - pull mode) . 2016.0 7.06 2.03 1. updated adc function pins of nuc123 qfn33 package type in section 4.3.1.3 , 4.3.2.3 and 4.4.1 . 2017.05.03 2.04 1. updated typical crystal application circuit for external 4~24 mhz high speed crystal in section 7.3.2.1 .
nuc123 may 3 , 201 7 page 99 of 99 rev. 2 . 0 4 nuc123 series datasheet important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usag e includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instrume nts, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, custome r shall indemnify the damages and liabilities thus incurred by nuvoton.

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